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preliminary user?s manual target cpu cores nu85ea nu85et ndu85etvxx memory controller NA85E535, nba85e535vxx document no. a15555ej2v0um00 (2nd edition) date published october 2002 n cp(n) printed in japan ? 2001
preliminary user?s manual a15555ej2v0um 2 [memo]
preliminary user?s manual a15555ej2v0um 3 notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. production process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed immediately after power-on for devices having reset function.
preliminary user ? s manual a15555ej2v0um 4 the export of this product from japan is regulated by the japanese government. to export this product may be prohibited without governmental license, the need for which must be judged by the customer. the export or re-export of this product from a country other than japan may also be prohibited without a license from that country. please call an nec sales representative. ? the information contained in this document is being issued in advance of the production cycle for the device. the parameters for the device may change before final production or nec corporation, at its own discretion, may withdraw the device prior to its production. ? not all devices/types available in every country. please check with local nec representative for availability and additional information. ? no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec corporation. nec corporation assumes no responsibility for any errors which may appear in this document. ? nec corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. no license, either express, implied or otherwise, is granted under any patents, c opyrights or other intellectual property rights of nec corporation or others. ? descriptions of circuits, software, and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. the incorporation of these circuits, software, and information in the design of the customer's equipment shall be done under the full responsibility of the customer. nec corporation assumes no responsibility for any losses incurred by the customer or third parties arising from the use of these circuits, software, and information. ? while nec corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. to minimize risks of damage or injury to persons or property arising from a defect in an nec semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. ? nec devices are classified into the following three quality grades: "standard", "special", and "specific". the specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. the recommended applications of a device depend on its quality grade, as indicated below. customers must check the quality grade of each device before using it in a particular application. standard: computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots special: transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) specific: aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. the quality grade of nec devices is "standard" unless otherwise specified in nec's data sheets or data books. if customers intend to use nec devices for applications other than those specified for standard quality grade, they should contact an nec sales representative in advance. m5d 98. 12
preliminary user ? s manual a15555ej2v0um 5 regional information some information contained in this document may vary from country to country. before using any nec product in your application, piease contact the nec office in your country to obtain a list of authorized representatives and distributors. they will verify: ? device availability ? ordering information ? product release schedule ? availability of related technical literature ? development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, ac supply voltages, and so forth) ? network requirements in addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. nec electronics inc. (u.s.) santa clara, california tel: 408-588-6000 800-366-9782 fax: 408-588-6130 800-729-9288 nec electronics hong kong ltd. hong kong tel: 2886-9318 fax: 2886-9022/9044 nec electronics hong kong ltd. seoul branch seoul, korea tel: 02-528-0303 fax: 02-528-4411 nec electronics shanghai, ltd. shanghai, p.r. china tel: 021-6841-1138 fax: 021-6841-1137 nec electronics taiwan ltd. taipei, taiwan tel: 02-2719-2377 fax: 02-2719-5951 nec electronics singapore pte. ltd. novena square, singapore tel: 253-8311 fax: 250-3583 nec do brasil s.a. electron devices division guarulhos-sp, brasil tel: 11-6462-6810 fax: 11-6462-6829 j02.4 nec electronics (europe) gmbh duesseldorf, germany tel: 0211-65 03 01 fax: 0211-65 03 327 sucursal en espa ? a madrid, spain tel: 091-504 27 87 fax: 091-504 28 60 v lizy-villacoublay, france tel: 01-30-67 58 00 fax: 01-30-67 58 99 succursale fran ? aise filiale italiana milano, italy tel: 02-66 75 41 fax: 02-66 75 42 99 branch the netherlands eindhoven, the netherlands tel: 040-244 58 45 fax: 040-244 45 80 branch sweden taeby, sweden tel: 08-63 80 820 fax: 08-63 80 388 united kingdom branch milton keynes, uk tel: 01908-691-133 fax: 01908-670-290
preliminary user?s manual a15555ej2v0um 6 major revisions in this edition (1/2) page description p.17 addition of description to 1.2 (2) page rom connection function pp.17, 18 addition of power-saving sdram connection function, caution , and remark to 1.2. (3) sdram connection function p.18 addition of 1.2 (5) dma acknowledge, chip select, and terminal count handling functions p.18 change of description in 1.2 (7) variable internal system clock function p.19 change of 1.3 symbol diagram p.20 change of 1.4.1 internal block diagram p.21 change of description in 1.4.2 (2) divider block p.23 addition of description to 1.4.2 (7) data read control block p.27 addition and change of description in 1.6 comparison with nt85e500 and nt85e502 pp.28 to 30 change of 2.1 pin function list p.31 addition of caution to 2.2.1 (1) (b) vsa25 to vsa0 p.34 addition of transfer response to table 2-5 transfer response p.35 addition of description and remark to 2.2.1 (2) (b) vpretr p.36 change of description in 2.2.1 (3) (a) vbclk p.36 addition of 2.2.1 (3) (b) vbclk2 p.37 change of description in 2.2.2 (2) ckmd1 and ckmd0 p.37 change of table 2-6 ckmd1 and dkmd0 pins p.39 addition of description to 2.2.3 (7) iordzr and iordzf p.39 addition of description to 2.2.3 (8) iowrz p.40 addition of caution to 2.2.3 (15) bcystz p.41 change of description in 2.2.3 (18) busclk p.41 addition of 2.2.3 (19) busclk2 pp.41, 42 addition of description to 2.2.3 (20) sdrasz , (21) sdcasz , (22) sdwez , (23) cke , and (24) dqm3 to dqm0 p.42 change of 2.2.3 (26) me7 to me0 to external memory connection pins p.43 addition of description to 2.2.4 (2) dmtcom3 to dmtcom0 , (4) dmactvm3 to dmactvm0 , (6) dmxtcm13 to dmxtcm10 and dmxtcm03 to dmxtcm00 , and (8) dmxczm13 to dmxczm10 and dmxczm03 to dmxczm00 p.44 addition of phtdin1, phtdin0, vptclk, phtdo1, and phtdo0 to 2.2.6 pins reserved by nec p.45 change of 2.3 connection of unused pins pp.46, 47 change of table 2-8 pin status in each operation mode pp.48, 49 addition of bcp, escn register n to table 3-1 control register list p.53 addition of 3.1.4 flyby transfer strobe control register (bcp) pp.64 to 66 addition of 3.1.9 setting register for mobileram expansion mode register n (escn) p.68 addition of 3.1.10 (1) recommended setting of speculative read function pp.69, 70 change of 3.1.11 bus mode control register (bmc) p.71 addition of figure 3-14 procedure of setting pdwn bit (1) p.71 addition of figure 3-15 procedure of clearing pdwn bit (0)
preliminary user?s manual a15555ej2v0um 7 major revisions in this edition (2/2) page description p.72 addition of figure 3-16 procedure of setting ckm1 and ckm0 bits pp.85, 86 change and addition of description in 3.3 stop function p.86 addition of 3.3 (2) timing of setting/releasing stop mode pp.87 to 90 addition of figure 3-27 timing of setting/releasing stop mode (without sdram setting) p.91 addition of caution to 3.4 bus hold function p.92 modification of figure 3-28 bus hold timing pp.93 to 98 addition of 3.5 cautions pp.99 to 102 addition of table 4-1 examples of memory access timing pp.104 to 118 modification of figure 4-1 example of sram access timing (a) to (i) and (k) to (o) , and addition of (j) pp.119 to 132 modification of figure 4-2 example of sdram access timing (a) to (l) and (n) , and addition of (m) pp.133 to 138 modification of figure 4-3 example of page rom access timing (a) to (d) , and addition of (e) and (f) pp.139 to 154 addition of figures 4-4 to 4-13 example of dma transfer timing (flyby transfer) pp.155 to 178 addition of figures 4-14 to 4-21 example of dma transfer timing (2-cycle transfer) p.179 modification of figure 4-22 sdram cbr refresh timing p.180 modification of figure 4-23 sdram self-refresh timing (stop timing) p.181 addition of figure 4-24 mobileram deep power down timing (stop timing) p.182 modification of figure 4-25 sdram mode register write operation timing p.183 addition of figure 4-26 mobileram expansion mode register write operation timing p.127 in old edition deletion of 5.1 test in peripheral test mode of nu85e p.186 addition of 5.2 notes on wiring test bus p.203 modification of figure a-1 example of connecting cpu core, NA85E535, and external memory (sram or sdram) the mark shows major revised points.
preliminary user?s manual a15555ej2v0um 8 introduction target readers this manual is intended for users who wish to understand the functions of the memory controllers NA85E535 and nba85e535vxx for the cbic cpu cores nu85ea, nu85et, and ndu85etvxx, and to design application systems using these memory controllers. ? NA85E535 (cb-10 family vx type): target cpu core (nu85ea, nu85et) ? nba85e535vxx (cb-12 family m type): target cpu core (ndu85etvxx) purpose this manual is intended to give users an understanding of the functions of the NA85E535 and nba85e535vxx. organization this manual consists of the following chapters. ? overview ? pin functions ? bus control function ? examples of memory access timing ? test function ? data flow how to read this manual it is assumed that the reader of this manual has general knowledge in the fields of electrical engineering, logic circuits, microcontrollers, sram, page rom, and sdram. to understand the overall functions of the NA85E535 and nba85e535vxx read this manual in the order of the contents. to learn the details of a function whose name is already known refer to appendix b general index . to learn the functions of the nu85ea refer to nu85e hardware user?s manual (a14874e) . to learn the functions of the nu85et and ndu85etv14 refer to nu85et hardware user?s manual (a15015e) . unless otherwise specified, the NA85E535 is treated as the representative memory controller in this manual. when using the nba85e535vxx, read the macro name of the memory controller (NA85E535) as ?nba85e535vxx? and read the macro name of the dma controller (na85e300) as ?nba85e300vxx?. in addition, the nu85ea is treated as the representative cpu core in this manual. when using the nu85et or ndu85etvxx, therefore, read the cpu core name as nu85et or ndu85etvxx.
preliminary user?s manual a15555ej2v0um 9 conventions data significance: higher digits on the left and lower digits on the right active low representation: xxxz (z suffixed to a pin or signal name) note : footnote for item marked with note in the text caution : information requiring particular attention remark : supplementary information numerical representation: binary ? xxxx or xxxxb decimal ? xxxx hexadecimal ? xxxxh prefix indicating power of 2 (address space and memory capacity): k (kilo) ? 2 10 = 1024 m (mega) ? 2 20 = 1024 2 g (giga) ? 2 30 = 1024 3 data type: word ? 32 bits halfword ? 16 bits byte ? 8 bits related documents the related documents indicated in this publication may include preliminary versions. however, preliminary versions are not marked as such. ? nu85e hardware user?s manual (a14874e) ? nu85et hardware user?s manual (a15015e) ? cb-10 family vx type nu85e, nu85et design manual (a15401e) ? cb-10 family vx type core library for cpu core, peripheral design manual (a15133e) ? how to use sdram user?s manual (j0123n note ) ? synchronous dram user?s manual (j0124n note ) note this is a document published by elpida memory, inc. (http://www.elpida- memory.com/). the related documents listed above are subject to change without notice. be sure to use the latest version of each document for designing.
preliminary user?s manual a15555ej2v0um 10 contents chapter 1 overview ............................................................................................................ ...............16 1.1 general ..................................................................................................................... ...................................16 1.2 features .................................................................................................................... ..................................17 1.3 symbol diagram .............................................................................................................. ...........................19 1.4 block diagram ............................................................................................................... .............................20 1.4.1 internal block diagram .................................................................................................... ................20 1.4.2 internal units ............................................................................................................ .......................21 1.5 system configuration example ................................................................................................ ................25 1.5.1 2-cycle transfer by dma (without flyby transfer) .......................................................................... ...25 1.5.2 flyby transfer by dma ..................................................................................................... ...............26 1.6 comparison with nt85e500 and nt85e502....................................................................................... ......27 chapter 2 pin functions ....................................................................................................... ...........28 2.1 pin function list ........................................................................................................... .............................28 2.2 pin functions............................................................................................................... ...............................31 2.2.1 cpu core connection pins .................................................................................................. ............31 2.2.2 initialization pins ....................................................................................................... ......................37 2.2.3 external memory connection pins........................................................................................... ........39 2.2.4 dma pins .................................................................................................................. ......................43 2.2.5 separate unit test mode pins .............................................................................................. ............44 2.2.6 pins reserved by nec ...................................................................................................... ..............44 2.3 connection of unused pins ................................................................................................... ...................45 2.4 pin status.................................................................................................................. ..................................46 chapter 3 bus control function ................................................................................................ 48 3.1 control registers ........................................................................................................... ............................48 3.1.1 bus cycle type configuration registers 0 and 1 (bct0 and bct1) .................................................50 3.1.2 address setting wait control register (asc) ............................................................................... .....51 3.1.3 bus cycle control register (bcc).......................................................................................... ...........52 3.1.4 flyby transfer strobe control register (bcp) .............................................................................. .....53 3.1.5 data wait control registers 0 and 1 (dwc0 and dwc1).................................................................54 3.1.6 page rom configuration register (prc)..................................................................................... ....56 3.1.7 sdram configuration register n (scrn) ..................................................................................... ...58 3.1.8 sdram refresh control register n (rfsn) ................................................................................... ...62 3.1.9 setting register for mobileram expansion mode register n (escn)...............................................64 3.1.10 line buffer control registers 0 and 1 (lbc0 and lbc1)..................................................................67 3.1.11 bus mode control register (bmc).......................................................................................... ..........69 3.1.12 local bus sizing control register (lbs) .................................................................................. .........73 3.1.13 dma flyby transfer wait control register (fwc)........................................................................... ....74 3.1.14 dma flyby transfer idle control register (fic)........................................................................... .......75 3.2 examples of memory connection............................................................................................... ..............76 3.2.1 example of sram connection ................................................................................................ ........76 3.2.2 example of page rom connection ............................................................................................ .....78 3.2.3 example of sdram connection............................................................................................... .......80 3.3 stop function ............................................................................................................... ............................85
preliminary user?s manual a15555ej2v0um 11 3.4 bus hold function ........................................................................................................... .......................... 91 3.5 cautions.................................................................................................................... .................................. 93 3.5.1 connection to vsb ......................................................................................................... ................ 93 3.5.2 designing high-speed circuit .............................................................................................. ............ 95 3.5.3 processing of data bus .................................................................................................... ............... 97 3.5.4 dma acknowledge/chip select handling function ........................................................................... 98 chapter 4 memory access timing examples............................................................................99 chapter 5 test function ....................................................................................................... ........186 5.1 separate unit test.......................................................................................................... .......................... 186 5.2 notes on wiring test bus .................................................................................................... ................... 186 chapter 6 data flow........................................................................................................... ............187 6.1 data flow for byte access (8 bits).......................................................................................... ............... 188 6.2 data flow for halfword access (16 bits) ..................................................................................... .......... 190 6.3 data flow for word access (32 bits) ......................................................................................... ............ 196 appendix a connection example ................................................................................................2 02 appendix b general index .................................................................................................... .......204
preliminary user?s manual a15555ej2v0um 12 list of figures (1/3) figure no. title page 1-1 example of connecting sram, page rom, and sdram ............................................................................. ...16 1-2 status transition of sdram access........................................................................................... ......................22 3-1 bus cycle type configuration registers 0 and 1 (bct0 and bct1).............................................................. ..50 3-2 address setting wait control register (asc) ................................................................................. ..................51 3-3 bus cycle control register (bcc) ............................................................................................ ........................52 3-4 flyby transfer strobe control register (bcp) ................................................................................ ..................53 3-5 data wait control registers 0 and 1 (dwc0 and dwc1) ......................................................................... .......54 3-6 page rom configuration register (prc) ....................................................................................... ..................56 3-7 example of control by ma6 to ma3 bits ....................................................................................... ....................57 3-8 sdram configuration register n (scrn)....................................................................................... ..................58 3-9 sdram refresh control register n (rfsn) ..................................................................................... ................62 3-10 setting register for mobileram expansion mode register n (escn) ............................................................ ..64 3-11 flow from setting escn and scrn register to register write operation....................................................... .66 3-12 line buffer control registers 0 and 1 (lbc0 and lbc1)...................................................................... ............67 3-13 bus mode control register (bmc) ............................................................................................ ........................70 3-14 procedure of setting pdwn bit (1) .......................................................................................... .........................71 3-15 procedure of clearing pdwn bit (0)......................................................................................... ........................71 3-16 procedure of setting ckm1 and ckm0 bits.................................................................................... ..................72 3-17 local bus sizing control register (lbs).................................................................................... .......................73 3-18 dma flyby transfer wait control register (fwc)............................................................................. ...............74 3-19 dma flyby transfer idle control register (fic) ............................................................................. ..................75 3-20 sram connection example 1.................................................................................................. .........................76 3-21 sram connection example 2.................................................................................................. .........................77 3-22 page rom connection example 1 (data bus width: 16 bits) .................................................................... ......78 3-23 page rom connection example 2 (data bus width: 8 bits) ..................................................................... .......79 3-24 example of 64mb sdram connection ........................................................................................... ..................80 3-25 operation of NA85E535 in stop mode......................................................................................... ...................85 3-26 operation of NA85E535 when stop mode is released ........................................................................... ......86 3-27 timing of setting/releasing stop mode (without sdram setting) .............................................................. ..87 3-28 bus hold timing ............................................................................................................ ....................................92 3-29 example of connection of memc and bus master in vsb multi-master configuration ....................................93 3-30 example of memory access timing ............................................................................................ ......................94 3-31 example of measures to relax data setup time ............................................................................... ..............95 3-32 processing of data bus..................................................................................................... ................................97 3-33 example of circuit selecting acknowledge/chip select signal (with na85e300) ............................................98 4-1 example of sram access timing............................................................................................... ....................104 4-2 example of sdram access timing .............................................................................................. ..................119 4-3 example of page rom access timing ........................................................................................... ................133 4-4 example of dma transfer timing (flyby transfer (using dmac with on-chip cpu core): sram external i/o) ...........................................139
preliminary user?s manual a15555ej2v0um 13 list of figures (2/3) figure no. title page 4-5 example of dma transfer timing (flyby transfer (using dmac with on-chip cpu core): external i/o sram)........................................... 143 4-6 example of dma transfer timing (flyby transfer (using dmac with on-chip cpu core): page rom external i/o (single transfer) .......... 145 4-7 example of dma transfer timing (flyby transfer (using dmac with on-chip cpu core): sdram external i/o (single transfer)............... 146 4-8 example of dma transfer timing (flyby transfer (using dmac with on-chip cpu core): external i/o sdram (single transfer).............. 147 4-9 example of dma transfer timing (flyby transfer (with na85e300): sram external i/o)........................ 148 4-10 example of dma transfer timing (flyby transfer (with na85e300): external i/o sram)........................ 150 4-11 example of dma transfer timing (flyby transfer (with na85e300): page rom external i/o) (single transfer (4 words)))......................... 152 4-12 example of dma transfer timing (flyby transfer (with na85e300): sdram external i/o) (single transfer (4 words))).............................. 153 4-13 example of dma transfer timing (flyby transfer (with na85e300): external i/o sdram) (single transfer (4 words))).............................. 154 4-14 example of dma transfer timing (2-cycle transfer (using dmac with on-chip cpu core): sram sram)................................................. 155 4-15 example of dma transfer timing (2-cycle transfer (using dmac with on-chip cpu core): sdram sdram)............................................ 160 4-16 example of dma transfer timing (2-cycle transfer (using dmac with on-chip cpu core): sram npb (single transfer/with speculative read/local bus size: 32 bits)).......................................... 165 4-17 example of dma transfer timing (2-cycle transfer (using dmac with on-chip cpu core): npb sram (single transfer/local bus size: 32 bits)) .............................................................................. 1 66 4-18 example of dma transfer timing (2-cycle transfer (using dmac with on-chip cpu core): npb npb (single transfer/during speculative read/local bus size: 32 bits)) ........................................ 167 4-19 example of dma transfer timing (2-cycle transfer (using dmac with on-chip cpu core): npb ram (single transfer/during speculative read/local bus size: 32 bits))........................................ 168 4-20 example of dma transfer timing (2-cycle transfer (with na85e300): sram sram) ............................. 169 4-21 example of dma transfer timing (2-cycle transfer (with na85e300): sdram sdram)........................ 174 4-22 sdram cbr refresh timing ................................................................................................... ...................... 179 4-23 sdram self-refresh timing (stop timing).................................................................................... .............. 180 4-24 mobileram deep power down timing (stop timing) ............................................................................. ..... 181 4-25 sdram mode register write operation timing ................................................................................. ............ 182 4-26 mobileram expansion mode register write timing ............................................................................. ......... 183 4-27 bmc register change timing (divided by 1 divided by 2) ........................................................................ 184 4-28 example of sram write access timing (if vbclk is divided by two to generate busclk) ...................... 185 5-1 wiring of test bus.......................................................................................................... ................................. 186 6-1 data, vsb, external data bus ................................................................................................ ........................ 187 6-2 data flow for byte access (little endian)................................................................................... .................... 188 6-3 data flow for byte access (big endian) ...................................................................................... ................... 189
preliminary user?s manual a15555ej2v0um 14 list of figures (3/3) figure no. title page 6-4 data flow for halfword access (little endian) ............................................................................... .................190 6-5 data flow for halfword access (big endian) .................................................................................. ................193 6-6 data flow for word access (little endian)................................................................................... ...................196 6-7 data flow for word access (big endian) ...................................................................................... ..................199 a-1 example of connecting cpu core, NA85E535, and external memory (sram or sdram) (when bus master other than cpu core is not used) .............................................................................. ....203
preliminary user?s manual a15555ej2v0um 15 list of tables table no. title page 2-1 vsbenz3 to vsbenz0 signals.................................................................................................. ...................... 31 2-2 vsctyp2 to vsctyp0 signals.................................................................................................. ...................... 31 2-3 vsseq2 to vsseq0 signals.................................................................................................... ........................ 32 2-4 start address for sequential transfer....................................................................................... ........................ 32 2-5 transfer response ........................................................................................................... ................................ 34 2-6 ckmd1 and ckmd0 pins ........................................................................................................ ......................... 37 2-7 lbs1 and lbs0 pins.......................................................................................................... ............................... 38 2-8 pin status in each operation mode ........................................................................................... ....................... 46 3-1 control register list ....................................................................................................... .................................. 48 3-2 row address output .......................................................................................................... ............................... 61 3-3 column address output....................................................................................................... ............................. 61 3-4 example of sdram refresh interval........................................................................................... ..................... 63 4-1 examples of memory access timing ............................................................................................ .................... 99 4-2 transfer response ........................................................................................................... .............................. 103
preliminary user?s manual a15555ej2v0um 16 chapter 1 overview 1.1 general the NA85E535 is a macro that controls external memory and includes an sram/external i/o controller, a page rom controller, and a synchronous dram (sdram) controller. this macro can start an external bus cycle to access various memories when it is connected to a cpu core via the vsb. when using the NA85E535, set the vsb data bus size to 32 bits regardless of the data bus width of the memory (set by using the bus size configuration register (bsc) register of the nu85ea). figure 1-1. example of connecting sram, page rom, and sdram asic vsb NA85E535 cpu core sram page rom sdram
chapter 1 overview preliminary user?s manual a15555ej2v0um 17 1.2 features (1) sram connection function one sram/external i/o controller is provided that controls access to the sram (or external i/o) located in all csn areas (n = 7 to 0). the major features of this sram/external i/o controller are as follows. ? minimum 2-states access ? insertion of up to seven data wait states by register setting ? insertion of up to three address setting wait states by register setting ? insertion of data wait by external pin input ? insertion of up to three idle cycle states by register setting ? 2-cycle transfer and flyby transfer by dma (sram external i/o, external i/o sram) supported (2) page rom connection function one page rom controller is provided that controls access to the page rom located in all csn areas. the major features of this page rom controller are listed below. ? minimum 2-state access ? on-page identification function change of address to be compared by register setting insertion of up to seven off-page/on-page data wait states by register setting ? read strobe signals (rdzr and rdzf) held active (low level) until a cycle in which the vsseq2 to vsseq0 signals, which indicate the end of sequential transfer, are 000, if a sequential access is requested by the cpu core. ? insertion of data wait by external pin input ? 2-cycle transfer and flyby transfer by dma (page rom external i/o) supported ? sram write cycle started if write cycle request is issued to csn area where page rom is located because the vsb data bus size is fixed to 32 bits, a vsb sequential access does not take place and on-page identification is not performed if a cache and an external bus master is not connected to the cpu core (however, access is executed on page if the speculative read function is used). an efficient page access can be made to page rom only when transfer is executed from page rom to cache in a system with cache mounted, or when speculative read is set. (3) sdram connection function four sdram controllers are provided that control access to the sdram located in the cs1, cs3, cs4, and cs6 areas. the major features of these sdram controllers are as follows. ? standard sdram (sdr sdram: single data rate sdram) or power-saving sdram (mobileram) can be connected. ? single-access-only can be activated (burst length = 1) (however, dummy accessing is executed by issuing a read/write command every clock if a continuous transfer is requested from a bus master, such as the cpu core, by vsseq2 to vsseq0 input). ? cas latency = 1, 2, and 3 supported ? insertion of up to three wait states by register setting ? execution of register write operation each time scrn register is accessed for write (n = 6, 4, 3, or 1). ? cbr (cas-before-ras) refresh command issued. ? 2-cycle transfer and flyby transfer by dma (sram external i/o, external i/o sram) supported
chapter 1 overview preliminary user?s manual a15555ej2v0um 18 caution sdr sdram and mobileram cannot be connected at the same time (must not be used together). connect either of them. remark unless otherwise specified, both sdr sdram and mobileram are referred to as ?sdram? in this manual. (4) dma flyby function this function allows the dma controller (dmac) connected to the vsb to transfer data to external i/o when data is read from sram, page rom, or sdram, and to transfer data to sram or sdram when data is read from the external i/o. up to four external i/os can be connected. up to seven data wait states and up to three idle states can be inserted by register setting. (5) dma acknowledge, chip select, and terminal count handling functions after receiving an acknowledge signal, chip select signal, and terminal count signal input in synchronization with the system clock (vbclk) and matching them with the actual dma memory cycle (handled), each signal is output in synchronization with the bus clock (busclk). (for the acknowledge signal and chip select signal, the active level is output only during flyby transfer. the inactive level is always output during 2-cycle transfer.) (6) speculative read/write buffer function a read buffer and a write buffer consisting of 4 words (128 bits) are provided. if speculative read is enabled by line buffer control registers 0 and 1 (lbc0 and lbc1), data of up to 4 words can be read from addresses whose lower 4 bits are 0h to fh. remark in this manual, ?32 bits? is defined as ?1 word? and ?4 words? is defined as ?1 line?. (7) variable internal system clock function the memory controller can operate with a clock (internal system clock) that is divided by 1, 2, 3, or 4 for the system clock (vbclk). the divided clock is output to an external device as bus clock by busclk pin. the division ratio is determined at reset, according to the input levels of the ckmd1 and ckmd0 pins (the division ratio can be changed, after reset, by setting the bmc register). remark only one internal system clock can be set for all memory controllers (it cannot be changed in each csn area (n = 7 to 0)). (8) separate unit test function the NA85E535 can be set in separate unit test mode according to the combination of the signals of the test and bunri pins and its internal circuitry can be tested by using the test bus of the NA85E535.
chapter 1 overview preliminary user?s manual a15555ej2v0um 19 1.3 symbol diagram vpdw (15:0) vbdi (31:0) vptclk in phtest in out phtdo (1:0) csz (7:0) ckmd (1:0) benz (3:0) refrqz selfref bcystz busclk stprq stpak mce a (25:0) rdzr iordzr waitz hldrqz hldakz dc (3:0) r di (31:0) vbdo (31:0) vpresz vsahld vslast vsseq (2:0) vswrite vsstz vaexreq vpstb vpubenz vpwrite vaack vpdr (15:0) vswait vpa (13:0) vsa (25:0) vsbenz (3:0) vsctyp (2:0) vdcsz (7:0) vbclk out out out in out out in out out in out out in in out out in in in in out out out in out in in in out in in in in in in in phtdin (1:0) in out in do (31:0) out sdrasz out sdcasz out sdwez out cke out dqm (3:0) out vacbrrq out rdzf out iordzf out iowrz out wrstz out in in in out in out in in out out in out out in dmtco (3:0) dmtcom (3:0) dmactv (3:0) dmactvm (3:0) dmxtco1 (3:0) dmxtco0 (3:0) dmxtcm1 (3:0) dmxtcm0 (3:0) dmxcsz1 (3:0) dmxcsz0 (3:0) dmxczm1 (3:0) dmxczm0 (3:0) out vpdv v2en in dc (3:0) f out vbresz in vpretr out lbs (1:0) in out out wrstbz wrz (3:0) mpxen in astbz out dstbz out mpxcz out mwaitz in vmlock out tbi (19:0) in out tbo (15:0) test in bunri in out me (7:0) vbclk2 in busclk2 out
chapter 1 overview preliminary user?s manual a15555ej2v0um 20 1.4 block diagram 1.4.1 internal block diagram vsb signal sram/external i/o controller page rom controller sdrasz sdwez sdcasz cke dqm3 to dqm0 divider block bus arbitration controller test bus interface block waitz rdzr rdzf wrz3 to wrz0 wrstbz iordzr iordzf iowrz a25 to a0 do31 to do0 di31 to di0 csz7 to csz0 benz3 to benz0 dc3f to dc0f wrstz phtdin1, phtdin0 phtdo1, phtdo0 phtest vptclk dmtco3 to dmtco0 dmactv3 to dmactv0 dmxtco03 to dmxtco00 dmxcsz03 to dmxcsz00 dmxtco13 to dmxtco10 dmxcsz13 to dmxcsz10 dmtcom3 to dmtcom0 dmactvm3 to dmactvm0 dmxtcm03 to dmxtcm00 dmxczm03 to dmxczm00 dmxtcm13 to dmxtcm10 dmxczm13 to dmxczm10 vaexreq stprq stpak vacbrrq vaack refrqz hldrqz hldakz selfref sdram controller vbdo31 to vbdo0 vbdi31 to vbdi0 internal bus internal bus control block data write control block data read control block dma status signal controller busclk dc3r to dc0r address/data/ chip select controller lbs0 npb signal mce ckmd0 ckmd1 v2en lbs1 vbclk mpxen register block vmlock tbi19 to tbi0 tbo15 to tbo0 test bunri me7 to me0 busclk2 divider block vbclk vbclk2
chapter 1 overview preliminary user?s manual a15555ej2v0um 21 1.4.2 internal units (1) register block this block incorporates the registers that control the bus cycle. these registers are used to specify the operation of each controller, such as selecting an external memory type for each csn area and setting the number of idle/wait states (n = 7 to 0). the registers are read or written via the npb. (2) divider block this block divides system clocks (vbclk, vbclk2) input from external devices (the register that sets the division ratio is in the register block). (3) sram/external i/o controller and page rom controller these controllers control reading and writing of sram, external i/o, and page rom. they control access to all csn areas (n = 7 to 0). (4) sdram controllers these controllers control read/write access to sdram, the register write cycle, and refresh. four sdram controllers are available, corresponding to each of the cs1, cs3, cs4, and cs6 areas. commands issued to initialize sdram and to access memory (including commands that select pages and banks) are explained next (for the timing, refer to figure 4-2 example of sdram access timing ).
chapter 1 overview preliminary user?s manual a15555ej2v0um 22 figure 1-2. status transition of sdram access note 1 note 3 note 2 all-bank precharge commmand (power-on, refresh) bank a precharge command bank a active command read/write command bank b active command on-page access bank a active command bank a active command bank b read/write command bank a read/write command bank a read/write command bank a precharge command bank change page change read/write command bank change notes 1. an all-bank precharge command is always issued to sdram after power application and bus hold, or during refresh. when accessing sdram after this command has been issued, therefore, an active command and a read/write command are issued in that order. 2. if the page has been changed, a precharge command, active command, and read/write command are issued in that order. 3. if the bank has been changed, an active command and a read/write command are issued in that order to the bank to be accessed next. a precharge command is issued to the bank accessed immediately before the bank that is currently being accessed, immediately after the read/write command has been issued.
chapter 1 overview preliminary user?s manual a15555ej2v0um 23 (5) address/data/chip select controller this controller controls the address and data bus signals that are output to the memory, and input/output of various control signals, in synchronization with the internal system clock (busclk). (6) bus arbitration controller this controller controls the bus mastership. because the NA85E535 serves as a bus master, it asserts bus request signals (vaexreq and vacbrrq) at the following timing. ? vaexreq signal: when a stop mode request (stprq signal) is generated by the cpu core note when a self-refresh request (selfref signal) is generated when an external bus hold request (hldrqz signal) is generated ? vacbrrq signal: when a cbr refresh request is generated when an sdram mode register write command is issued note when the NA85E535 acknowledges the stprq signal, it outputs an acknowledge signal (stpak) to the cpu core and stops operation (refer to 3.3 stop function for details). when the NA85E535 acknowledges the stprq signal while sdram is connected to it, the memory controller executes a self-refresh cycle and then outputs the stpak signal (refer to figure 4-23 sdram self-refresh timing (stop timing) ). (7) data read control block this block controls the local bus (bus connected from the NA85E535 to the external memory) in response to a data read access from the vsb. it has a read buffer of one address stage and 4-word data 32 bits and controls speculative read operations. the speculative read condition can be specified by using the lbc0 and lbc1 registers. the read buffer discards its contents under the following conditions. ? writing to bct0 or bct1 register ? writing to lbs register ? writing to lbc0 or lbc1 register ? generation of bus hold ? generation of dma flyby cycle (not dependent on cs space) ? memory write access to line address speculatively read if data is written to the npb during a speculative read operation, a retry request is generated by the vpretr signal. the speculative read range is the addresses (xxxxxx0h to xxxxxxfh) on the same line as the address that has been accessed (critical first access method). for example, addresses ?xxxxx00h?, ?xxxxx04h?, and ?xxxxx01h? are accessed in the following sequence, and data is loaded to the read buffer (when speculative read is executed with the local bus size of 32 bits). ? when accessing address ?xxxxx00h?: xxxxx00h xxxxx04h xxxxx08h xxxxx0ch ? when accessing address ?xxxxx04h?: xxxxx04h xxxxx08h xxxxx0ch xxxxx00h ? when accessing address ?xxxxx01h?: xxxxx01h xxxxx05h xxxxx09h xxxxx0dh remark critical first access method is where the data necessary first is leaded when data of one line (4- word data equivalent to address ?xxxxxx0h to xxxxxxfh?) is loaded from the external memory.
chapter 1 overview preliminary user?s manual a15555ej2v0um 24 (8) data write control block this block controls the local bus in response to a data write access from the vsb. it has a write buffer of four address stages, four chip select stages, and four data stages 32 bits. this write buffer has four stages. if a write request is made when the buffer is full, a wait response continues to be output to the vsb until a vacancy is created in the buffer (until the cycle is completed once). (9) internal bus control block this block controls the internal bus using the signals from the read control block and write control block. the internal bus is connected from the internal bus control block to each of the internal controllers of the NA85E535 (the local bus is connected from the NA85E535 to the external memory). local bus sizing is performed in this block. the width of the bus to which an external bus is to be connected can be set to 32, 16, or 8 bits by using the lbs register in each csn area. when the data bus width is set to 16 or 32 bits, the lower address (a0 or a1, a0) cannot be used. (10) dma status signal controller this controller outputs the status signals from the internal dmac of the cpu core or an external dmac connected to the cpu core (such as the na85e300) to the external device in accordance with the bus cycle of the NA85E535. (11) test bus interface block this block interfaces the signals that test the NA85E535.
chapter 1 overview preliminary user?s manual a15555ej2v0um 25 1.5 system configuration example 1.5.1 2-cycle transfer by dma (without flyby transfer) asic v s b cpu core NA85E535 external control signal external bus master note 2 external data sram, external i/o page rom sdram note 1 external address notes 1. sdram with 11 to 13 row address lines, eight to 11 column address lines, and a cas latency of 1 to 3 can be connected to the NA85E535. 2. the NA85E535 has an external bus master arbitration function that is controlled by the hldrqz and hldakz signals.
chapter 1 overview preliminary user?s manual a15555ej2v0um 26 1.5.2 flyby transfer by dma asic v s b cpu core NA85E535 sram, external i/o external i/o external bus master note 2 page rom sdram note 1 external data external address note 3 external control signal notes 1. sdram with 11 to 13 row address lines, eight to 11 column address lines, and a cas latency of 1 to 3 can be connected to the NA85E535. 2. the NA85E535 has an external bus master arbitration function that is controlled by the hldrqz and hldakz signals. 3. if the external i/o has a chip select function, the cszn, dmactvmx, dmxczm1x, and dmxczm0x pins are used (n = 7 to 0, x = 3 to 0).
chapter 1 overview preliminary user?s manual a15555ej2v0um 27 1.6 comparison with nt85e500 and nt85e502 the NA85E535 has a functionally enhanced configuration in that it is connected to four additional nt85e502 sdram controllers as compared with the nt85e500 external memory controller. the differences from the nt85e500 and nt85e502, and the enhanced functions of the nt85e535 are listed below. ? enables operation with the clock (internal system clock) which is divided by 1, 2, 3, or 4 for the system clock (vbclk) ? controls address bus signals and data bus signals that are output from the NA85E535 to the memory, and i/o of various control signals in synchronization with the internal system clock. ? can connect sdram with 13 row address lines and 11 column address lines (the nt85e502 can connect sdram with 12 row address lines and 10 column address lines). ? cas latency can be set to 1 to 3 during a read operation, by using sdram configuration register n (scrn) (the latency of the nt85e502 is set to 2 or 3). ? write access to the same page/bank of sdram is shorter by two clocks than that of the nt85e502. ? mobileram can be connected. ? read buffer of 4 words is incorporated so that speculative read operations can be executed. ? four stages (128 bits) write buffer is incorporated. ? local bus sizing control register (lbs) is provided to change the size of the bus from vsb (32 bits) inside the NA85E535, in accordance with the data bus width of the memory to be accessed. ? can start a dma flyby cycle for sdram. ? can set the number of data wait cycles and the number of idle wait cycles during dma flyby transfer.
preliminary user?s manual a15555ej2v0um 28 chapter 2 pin functions 2.1 pin function list (1/3) pin name i/o function vdcsz7 to vdcsz0 input chip select input (for vsb) vsa25 to vsa0 input address input (for vsb) vsbenz3 to vsbenz0 input byte enable input (for vsb) vsctyp2 to vsctyp0 input bus cycle status i nput (for vsb) vbdo31 to vbdo0 input data input (for vsb) vbdi31 to vbdi0 output data output (for vsb) vpresz input system reset input (for vsb) vsseq2 to vsseq0 input sequential status input (for vsb) vswrite input read/write status input (for vsb) vsstz input transfer start input (for vsb) vaexreq output bus mastership request output other than cbr refresh (for vsb) vacbrrq output bus mastership request output of cbr refresh (for vsb) vmlock output bus lock output vaack input bus mastership acknowledge input (for vsb) vswait output wait response output (for vsb) vsahld output address hold response output (for vsb) vslast output write response output (for vsb) vpstb input data strobe input (for npb) vpretr output retry request output (for npb) vpubenz input upper byte enable input (for npb) vpa13 to vpa0 input address input (for npb) vpwrite input write access strobe input (for npb) vpdw15 to vpdw0 input data input (for npb) vpdr15 to vpdr0 output data output (for npb) vpdv output data output (vpdr15 to vpdr0) control output (for npb) vbclk input system clock input (for internal system clock, busclk si gnal generation) vbclk2 input system clock input (for busclk2 signal generation) stprq input stop mode request input cpu core connection pins stpak output acknowledge output in response to stprq input mce input men bit reset value control input of bct0 and bct1 registers (n = 7 to 0) ckmd1, ckmd0 input reset value control input of bmc register lbs1, lbs0 input reset value control input of lbs register initialization pins v2en input vsb specification selection input
chapter 2 pin functions preliminary user?s manual a15555ej2v0um 29 (2/3) pin name i/o function a25 to a0 output external memory address output di31 to di0 input external memory data input do31 to do0 output external memory data output rdzr output sram/page rom read strobe output (output at rising edge of busclk signal) rdzf output sram/page rom read strobe output (output at falling edge of busclk signal) wrz3 to wrz0 output sram/external i/o write strobe output wrstbz output sram/external i/o write strobe output iordzr output external i/o read strobe output (output at rising edge of busclk signal) iordzf output external i/o read strobe output (output at falling edge of busclk signal) iowrz output external i/o write strobe output waitz input wait request input hldrqz input external bus hold request input hldakz output external bus hold request acknowledge output dc3r to dc0r, dc3f to dc0f output data bus control output csz7 to csz0 output chip select output benz3 to benz0 output byte enable output bcystz output bus cycle start status output refrqz output refresh status output selfref input self-refresh request input busclk output bus clock output (generated from vbclk) busclk2 output bus clock output (generated from vbclk2) sdrasz output sdram row address strobe output sdcasz output sdram column address strobe output sdwez output sdram data write enable output cke output clock enable output dqm3 to dqm0 output data mask output wrstz output read/write status output of memory cycle external memory connection pins me7 to me0 output men bit value output of bct0 and bct1 registers (n = 7 to 0) dmtco3 to dmtco0 input terminal count input from internal dmac (dmac connected to cpu core) dmtcom3 to dmtcom0 output terminal count output of internal dmac cycle dmactv3 to dmactv0 input acknowledge signal (dmaack) input from internal dmac dma pins dmactvm3 to dmactvm0 output acknowledge signal (dmaack) output of internal dmac cycle
chapter 2 pin functions preliminary user?s manual a15555ej2v0um 30 (3/3) pin name i/o function dmxtco13 to dmxtco10, dmxtco03 to dmxtco00 input terminal count input from na85e300 (external dmac connected to cpu core) dmxtcm13 to dmxtcm10, dmxtcm03 to dmxtcm00 output terminal count output of na85e300 cycle dmxcsz13 to dmxcsz10, dmxcsz03 to dmxcsz00 input chip select signal input from na85e300 dma pins dmxczm13 to dmxczm10, dmxczm03 to dmxczm00 output chip select signal output of na85e300 cycle tbi19 to tbi4 input shift data input for separate unit test tbi3 input reset input for separate unit test tbi2 input clock input for separate unit test tbi1 input chip select input for separate unit test tbi0 input enable input for separate unit test tbo15 to tbo0 output shift data output for separate unit test bunri input bunri input for separate unit test pins for separate unit test mode test input test input for separate unit test mpxen input phtest input phtdin1, phtdin0 input vptclk input reserved by nec (input a low level to this pin) vbresz input mwaitz input reserved by nec (input a high level to this pin) astbz output dstbz output mpxcz output pins reserved by nec phtdo1, phtdo0 output reserved by nec (leave these pins open)
chapter 2 pin functions preliminary user?s manual a15555ej2v0um 31 2.2 pin functions 2.2.1 cpu core connection pins for details of each pin, refer to nu85e hardware user?s manual (a14874e) . (1) pins for vsb (a) vdcsz7 to vdcsz0 (input) these are chip select pins. they input the vdcszn signal for the csn area set by the chip area select control registers (csc0 and csc1) of the cpu core (n = 7 to 0). for details, refer to nu85e hardware user?s manual (a14874e) . (b) vsa25 to vsa0 (input) these pins form an address input bus for the vsb. caution the NA85E535 does not support the vma27 and vma26 pins of the target cpu core and the vma27 and vma26 pins of the na85e300 (nor does it support the vma28 to vma26 pins of the nx85e2x (under development)). therefore, up to 64 mb of space is supported for one cs area. (c) vsbenz3 to vsbenz0 (input) these pins are active-low pins and indicate the valid byte data of the data bus (vbdi31 to vbdi0 and vbdo31 to vbdo0) divided into four. table 2-1. vsbenz3 to vsbenz0 signals active (low level) signal valid byte data vsbenz3 vbdi31 to vbdi24, vbdo31 to vbdo24 vsbenz2 vbdi23 to vbdi16, vbdo23 to vbdo16 vsbenz1 vbdi15 to vbdi8, vbdo15 to vbdo8 vsbenz0 vbdi7 to vbdi0, vbdo7 to vbdo0 (d) vsctyp2 to vsctyp0 (input) these input pins indicate the current bus cycle status. table 2-2. vsctyp2 to vsctyp0 signals vsctyp2 vsctyp1 vsctyp0 bus cycle status 0 0 0 opcode fetch 0 0 1 data access 0 1 0 misalign access 0 1 1 read-modify-write access 1 0 0 fetching opcode of destination address of branch instruction 1 1 0 2-cycle dma transfer 1 1 1 flyby dma transfer 1 0 1 (reserved for future function expansion) remark 0: low-level input, 1: high-level input
chapter 2 pin functions preliminary user?s manual a15555ej2v0um 32 (e) vbdo31 to vbdo0 (input) these pins form a data bus that inputs data from a macro connected to the vsb. (f) vbdi31 to vbdi0 (output) these pins form a data bus that outputs data to a macro connected to the vsb. (g) vpresz (input) this pin inputs the system reset signal output by the cpu core. this signal asynchronously resets all registers (register settings are also reset). (h) vsseq2 to vsseq0 (input) these pins input a sequential status that indicates the transfer size during burst transfer. they indicate ?length of burst transfer? on starting burst transfer, ?continuous? during burst transfer, and ?single transfer? at the end of burst transfer. table 2-3. vsseq2 to vsseq0 signals vsseq2 vsseq1 vsseq0 sequential status 0 0 0 single transfer 0 0 1 continuous (indicates that the next transfer address is related to the current transfer address) note 0 1 0 continuous 4 times (length of burst transfer: 4) 0 1 1 continuous 8 times (length of burst transfer: 8) 1 0 0 continuous 16 times (length of burst transfer: 16) 1 0 1 continuous 32 times (length of burst transfer: 32) 1 1 0 continuous 64 times (length of burst transfer: 64) 1 1 1 continuous 128 times (length of burst transfer: 128) note this is output in the middle of continuous transfer of 2 times, or 4, 8, 16, 32, 64, or 128 times. remark 0: low-level input, 1: high-level input during sequential transfer, start transfer from the start address shown in table 2-4, according to the ?number of transfers? value. table 2-4. start address for sequential transfer vsseq2 vsseq1 vsseq0 number of transfers start address 0012 vsa25 to vsa0 = x,x,x,x,x,x,x,x,x,x,x,x,x,x,x,x,x,x,x,x,x,x,x,0,0,0 0104 vsa25 to vsa0 = x,x,x,x,x,x,x,x,x,x,x,x,x,x,x,x,x,x,x,x,x,x,0,0,0,0 0118 vsa25 to vsa0 = x,x,x,x,x,x,x,x,x,x,x,x,x,x,x,x,x,x,x,x,x,0,0,0,0,0 10016 vsa25 to vsa0 = x,x,x,x,x,x,x,x,x,x,x,x,x,x,x,x,x,x,x,x,0,0,0,0,0,0 10132 vsa25 to vsa0 = x,x,x,x,x,x,x,x,x,x,x,x,x,x,x,x,x,x,x,0,0,0,0,0,0,0 11064 vsa25 to vsa0 = x,x,x,x,x,x,x,x,x,x,x,x,x,x,x,x,x,x,0,0,0,0,0,0,0,0 1 1 1 128 vsa25 to vsa0 = x,x,x,x,x,x,x,x,x,x,x,x,x,x,x,x,x,0,0,0,0,0,0,0,0,0 remark 0: low-level input, 1: high-level input
chapter 2 pin functions preliminary user?s manual a15555ej2v0um 33 when using the read buffer (when ?speculative read? is specified by the lbc0 and lbc1 registers), transfer may not be executed correctly if it is started from an address other than the start addresses shown in table 2-4. if the address sequence of the sequential transfer target is ?xxxxx14h xxxxx18h xxxxx1ch xxxxx20h?, for example, the address sequence in which an access is actually made is ?xxxxx14h xxxxx18h xxxxx1ch xxxxx10h?. this means that transfer returns to the first address (xxxxx10h) on the same line. this is because data (4 words) on the same line is always read when speculative read is executed. when the read buffer is not used (when ?no speculative read? is specified by the lbc0 and lbc1 registers), transfer is correctly executed even if it is started from an address other than those listed in table 2-4. (i) vswrite (input) this input pin indicates the transfer direction. a high level is input to this pin during write. (j) vsstz (input) this input pin indicates the start of transfer. (k) vaexreq (output) this pin outputs a bus mastership request signal as a result of a cause other than an sdram cbr refresh. the vaexreq signal becomes active (high-level output) in the following cases. ? if a stop mode request (stprq signal) is generated from the cpu core ? if a self-refresh request (selfref signal) is generated ? if an external bus hold request (hldrqz signal) is generated (l) vacbrrq (output) this pin outputs a bus mastership request signal as a result of an sdram cbr refresh. the vacbrrq signal is also output when the sdram mode register write command is executed. remark if no other bus master except the cpu core is used, or the vaexreq and vacbrrq signals and input the result to the vareq pin of the cpu core. (m) vaack (input) this pin inputs a signal that indicates that the bus mastership request signal (vareq) has been acknowledged. (n) vmlock (output) this output pin holds the bus mastership and is connected to the bus arbiter. it is used to prohibit suspension of transfer due to an access by another bus master, between the current transfer and the next transfer.
chapter 2 pin functions preliminary user?s manual a15555ej2v0um 34 (o) vswait (output) this pin indicates a wait response. it is connected to the vmwait pin of the cpu core. the wait response is output to the bus master to request more bus cycles, because preparation for outputting data is not completed. when this signal goes high, the bus cycle enters the wait status. this signal is asserted when a wait response, address hold response, disconnect response, or busy response is output (the disconnect response and busy response are output when the v2en bit of the bmc register is set to 1). (p) vsahld (output) this pin indicates an address hold response. it is connected to the vmahld pin of the cpu core. the address hold response is output to the bus master to request more bus cycles when preparation for outputting data is complete. this signal is asserted when the address hold response or busy response is output (the busy response is output when the v2en bit of the bmc register is set to 1). when this signal and vswait signal go high, the bus cycle enters the address hold status. in the address hold status, it is not necessary to latch an address because the address for data does not change even in the middle of the read/write cycle of that data. consequently, the circuit can be simplified. if 1 or more idle states are set in the NA85E535, the vsahld signal is asserted during the idle state at the end of the read cycle of sram, page rom, or sdram. (q) vslast (output) this pin indicates a write response. it is connected to the vmlast pin of the cpu core. this pin is used when the bus decoder requires a decode cycle. this signal is asserted when the disconnect response or busy response is output (the disconnect response and busy response are output when the v2en bit of the bmc register is set to 1). in a system in which two or more external slave devices are connected and selected by a bus decoder, decoding to select the bus slave is usually executed during non-sequential transfer. even if an attempt is made to change the slave device during sequential transfer such as burst transfer, therefore, a decode cycle to select the slave cannot be issued. in this case, the slave device outputs a last response to notify the bus master that the slave select signal will change. the bus master transfers the next bus cycle by non-sequential transfer if it has received the last response from the slave device, so that a decode cycle can be issued. table 2-5. transfer response vswait vsahld vslast transfer response 0 0 0 ready response (status where current transfer is complete) 1 0 0 wait response 1 1 0 address hold response (holds address and control signal) 1 0 1 disconnect response note 1 1 1 busy response note note these responses are output when the v2en bit of the bus mode control register (bmc) is set to 1 (the target cpu core does not have a disconnect response and a busy response). remarks 1. 0: low level, 1: high level 2. the NA85E535 does not have a last response.
chapter 2 pin functions preliminary user?s manual a15555ej2v0um 35 (2) pins for npb (a) vpstb (input) this pin inputs the data strobe of the vpdw15 to vpdw0 signals. (b) vpretr (output) this pin outputs a retry request for the npb. when a write access is made to the bus mode control register (bmc) or when a write request is issued to the npb register of the NA85E535 while memory is being accessed, a retry request is issued. remark with the target cpu core, the retry request by the vpretr signal is not valid unless a high level is input to the vpdact pin. therefore, connect an address decoder that outputs a high level to the vpdact pin while all the on-chip npb registers of the NA85E535 are being accessed to the cpu core, in the same manner as the other npb peripheral macros (this address decoder does not have to be connected to the nx85e2x (under development)). (c) vpubenz (input) this is the upper byte enable input pin. a low level is input to this pin when halfword data is accessed or when an odd address is accessed for byte data. input a high level to this pin to access an even address in byte units. (d) vpa13 to vpa0 (input) these pins input an address for the npb. specify the lower 14 bits of the address. (e) vpwrite (input) this pin inputs the write access strobe of the vpdo15 to vpdo0 signals. input a high level to this pin during write. (f) vpdw15 to vpdw0 (input) these pins form a bus that inputs data from the cpu core. (g) vpdr15 to vpdr0 (output) these pins form a bus that outputs data to the cpu core. (h) vpdv (output) this pin outputs a signal that controls the data output (vpdr15 to vpdr0). it outputs a high level during read. when a bidirectional data bus is configured, this pin is connected to the enable pin of the three- state buffer connected to the data bus to control data output.
chapter 2 pin functions preliminary user?s manual a15555ej2v0um 36 (3) system control pins (a) vbclk (input) this pin inputs the system clock. input a stable clock with a duty factor of 50% from the external clock generator to this pin. (b) vbclk2 (input) this pin inputs a system clock that is used to generate the busclk2 clock. to improve the ac specification of the bus clock of a cbic product, input a clock adjusting the delay value to the vbclk signal. cautions 1. when the busclk2 signal is not used, clock input to the vbclk2 pin is not necessary (input a low level). however, be sure to input a clock to the vbclk pin, regardless of whether the busclk and busclk2 signals are used or not. 2. use the same clock generator for for both the vbclk and vbclk2 pins (use the common clock source). 3. the ac specification is defined for the delay difference between the vbclk and vbclk2 signals (contact nec for details). remark the busclk signal that uses the vbclk signal as a source clock is output to an external device of the NA85E535 and is also used for the internal circuit. therefore, the clock skew with the bus master of vsb must be adjusted and the delay value of the vbclk signal input to the NA85E535 cannot be made extremely faster than other macros. in contrast, the busclk2 signal, which uses the vbclk2 signal as a source clock, is a signal dedicated for the external output. it is therefore not necessary to adjust the clock skew of the clock input to the vbclk2 pin with the other macros on the vsb (the output delay value of the bus clock output from a cbic product can be improved). (c) stprq (input) this pin inputs a hardware/software stop mode request from the cpu core. (d) stpak (output) this pin inputs an acknowledge signal to the cpu core that has received the stprq signal.
chapter 2 pin functions preliminary user?s manual a15555ej2v0um 37 2.2.2 initialization pins caution do not change the input level of the following pins during operation (fix the input level). otherwise, the operation is not guaranteed. (1) mce (input) this pin enables operation of the NA85E535 at reset. depending on the input level of this pin, the value of the men bits of the bct0 and bct1 register at reset (default value) changes as follows (n = 7 to 0). ? low level: 0 (operation of the NA85E535 in the csn area is disabled (no response to the cpu core)) ? high level: 1 (operation of the NA85E535 in the csn area is enabled) make sure that the input level of this pin does not change before and after reset. (2) ckmd1 and ckmd0 (input) these input pins are used to select the division ratio of the bus clock (busclk/busclk2) to the system clock (vbclk/vbclk2) input from an external source after reset (the divided vbclk signal is also used as an internal system clock). depending on the input level of these pins, the value of the ckm1 and ckm0 bits of the bmc register (default value) changes as follows. table 2-6. ckmd1 and ckmd0 pins input level of ckmd1 and ckmd0 pins value of ckm1 and ckm0 bits after reset (default value) ckmd1 ckmd0 ckm1 bit ckm0 bit division ratio of busclk/busclk2 signal for vbclk/vbclk2 signal low level low level 0 0 1/1 (vbclk/vbclk2 is divided by 1.) low level high level 0 1 1/2 (vbclk/vbclk2 is divided by 2.) high level low level 1 0 1/3 (vbclk/vbclk2 is divided by 3.) high level high level 1 1 1/4 (vbclk/vbclk2 is divided by 4.) make sure that the input levels of these pins do not change before and after reset.
chapter 2 pin functions preliminary user?s manual a15555ej2v0um 38 (3) lbs1 and lbs0 (input) these pins are used to set the data bus width for the memory to be accessed at reset. depending on the input levels of these pins, the value of the lbs register at reset (default value) changes as follows. table 2-7. lbs1 and lbs0 pins input level of lbs1 and lbs0 pins lbs1 lbs0 value of lbs register at reset (default value) 0 0 aaaah (data bus width: 32 bits) 0 1 5555h (data bus width: 16 bits) 10 11 0000h (data bus width: 8 bits) remark 0: low-level input, 1: high-level input make sure that the input level of this pin does not change before and after reset. (4) v2en (input) this pin selects the specification of the vsb that connects the NA85E535. set this pin in accordance with the cpu core used. input a low level to this pin if a cpu core specified in this manual is connected. ? nu85ea, nu85et, ndu85etvxx: 0 (low-level input) ? nx85e2x (under development): 1 (high-level input) depending on the input level of this pin, the value of the v2en bit of the bmc register at reset (default value) changes as follows. ? low-level input: 0 (conforms to vsb specifications) ? high-level input: 1 (conforms to vsb2 specifications (support of bus reset, disconnect response, and busy response)) make sure that the input level of this pin does not change before and after reset.
chapter 2 pin functions preliminary user?s manual a15555ej2v0um 39 2.2.3 external memory connection pins (1) a25 to a0 (output) these pins form an address bus for external memory. (2) di31 to di0 (input) these pins form a data input bus for external memory. (3) do31 to do0 (output) these pins form a data output bus for external memory. (4) rdzr and rdzf (output) these pins output read strobe signals to make the sram and page rom active. the rdzr signal is asserted (low-level output) at the rising edge of the busclk signal, and the rdzf signal is asserted (low-level output) at the falling edge of the busclk signal. when connecting a memory, and the rdzr and rdzf signals and use the resultant signal. (5) wrz3 to wrz0 (output) these pins output write strobe signals to make the sram and external i/o active. wrz3 ? for do31 to do24 wrz2 ? for do23 to do16 wrz1 ? do15 to do8 wrz0 ? do7 to do0 (6) wrstbz (output) this pin outputs a write strobe signal to make the sram and external i/o active. this signal is the result of anding wrz3 to wrz0. (7) iordzr and iordzf (output) these pins output read strobe signals to make the external i/o active in the dma flyby cycle. the iordzr signal is asserted (low-level output) at the rising edge of the busclk signal and the iordzf signal is asserted (low-level output) at the falling edge of the busclk signal. the iordzr signal and the iordzf signals perform the same operation as the rdzr signal and rdzf signal, respectively, in a cycle other than the dma flyby cycle, only when the ioen bit of the flyby transfer strobe control register (bcp) is set to 1 (they do not operate when the ioen bit is cleared to 0). when connecting an external i/o, and the iordzr and iordzf signals and use the resultant signal. (8) iowrz (output) this pin outputs a write strobe signal to make the external i/o active in the dma flyby cycle. it is asserted (low-level output) at the falling edge of the busclk signal. the iowrz signal performs the same operation as the wrstb signal in a cycle other than the dma flyby cycle only when the ioen bit of the flyby transfer strobe control register (bcp) is set to 1 (it does not operate when the ioen bit is cleared to 0). (9) waitz (input) this pin inputs a wait request from external memory.
chapter 2 pin functions preliminary user?s manual a15555ej2v0um 40 (10) hldrqz (input) this pin inputs a bus hold request from the external device. it must be kept active during bus hold. (11) hldakz (output) this pin outputs a bus hold acknowledge signal to an external device. it indicates that bus hold is enabled. (12) dc3r to dc0r and dc3f to dc0f (output) these output pins control the direction of the i/o buffer of the data bus. dc3r, dc3f ? for di31 to di24, do31 to do24 dc2r, dc2f ? for di23 to di16, do23 to do16 dc1r, dc1f ? for di15 to di8, do15 to do8 dc0r, dc0f ? for di7 to di0, do7 to do0 these pins output a high level during read and flyby transfer by dma. the dcnr signal is asserted (high-level output) at the rising edge of the busclk signal, and the dcnf signal is asserted (high-level output) at the falling edge of the busclk signal (n = 3 to 0). when connecting an external i/o, and the dcnr and dcnf signals and use the resultant signal. (13) csz7 to csz0 (output) these are chip select output pins. they output the value input to the vdcsz7 to vdcsz0 pins. csz7 ? for cs7 area csz6 ? for cs6 area csz5 ? for cs5 area csz4 ? for cs4 area csz3 ? for cs3 area csz2 ? for cs2 area csz1 ? for cs1 area csz0 ? for cs0 area (14) benz3 to benz0 (output) these are byte enable output pins. they output the value input to the vmbenz3 to vmbenz0 pins of the cpu core. (15) bcystz (output) this pin indicates the bus cycle start status. caution a glitch is generated when sdram is successively accessed. therefore, avoid circuit configuration in which an operation is performed in synchronization with an edge of the bcystz signal (there is no problem when sram or page rom is accessed).
chapter 2 pin functions preliminary user?s manual a15555ej2v0um 41 (16) refrqz (output) this pin indicates the execution status of a refresh cycle to sdram. it outputs a low level while the refresh cycle is being executed. if this pin goes low during a bus hold, it indicates that a refresh request has been issued to the external bus master. (17) selfref (input) this pin inputs a self-refresh request. the input level of this pin indicates the presence or absence of the self-refresh request. ? low-level input: no self-refresh request has been generated. ? high-level input: self-refresh request has been generated. (18) busclk (output) this pin outputs the bus clock generated from the vbclk signal. it outputs a clock with the division ratio set by the ckmd1 and ckmd0 pins or the bus mode control register (bmc). the bus clock output from this pin is identical to the internal system clock. (19) busclk2 (output) this pin outputs the bus clock generated from the vbclk2 signal. the theoretical operation of this pin is the same as the busclk pin. however, the delay value of this pin is designed lower than that of the busclk signal inside the NA85E535, use the clock output from this pin to improve the bus clock output delay. (20) sdrasz (output) this pin outputs a row address strobe signal for sdram. this pin always outputs a high level if sdram is not set as a memory connected (by the bct0 and bct1 registers). (21) sdcasz (output) this pin outputs a column address strobe signal for sdram. this pin always outputs a high level if sdram is not set as a memory connected (by the bct0 and bct1 registers). (22) sdwez (output) this pin outputs a data write enable signal for sdram. this pin always outputs a high level if sdram is not set as a memory connected (by the bct0 and bct1 registers). (23) cke (output) this pin outputs a clock enable signal for sdram. it outputs an inactive level (low level) in the self-refresh cycle or during flyby transfer from sdram to external i/o (tf state). this pin always outputs a high level if sdram is not set as a memory connected (by the bct0 and bct1 registers).
chapter 2 pin functions preliminary user?s manual a15555ej2v0um 42 (24) dqm3 to dqm0 (output) these pins output data mask signals for sdram. they output the same value as the vmbenz3 to vmbenz0 signals of the cpu core while a write command is being executed. all these pins output a low level while a read command is being executed. this pin always outputs a high level if sdram is not set as a memory connected (by the bct0 and bct1 registers). (25) wrstz (output) this pin outputs the read/write status signal of a memory access cycle. it outputs a low level in the write cycle. (26) me7 to me0 (output) these pins output the value of the men bits of the bct0 and bct1 registers (n = 7 to 0). depending on the value of the men bits, the operation of the NA85E535 in each csn area can be enabled or disabled.
chapter 2 pin functions preliminary user?s manual a15555ej2v0um 43 2.2.4 dma pins (1) dmtco3 to dmtco0 (input) these pins input a terminal count from the internal dmac (of the cpu core). (2) dmtcom3 to dmtcom0 (output) these pins output the terminal count of the internal dmac cycle. if the dma transfer cycle issued by the on-chip dmac is transfer involving the terminal counter (dmtcon), these pins output a high level during the first 1busclk period when the NA85E535 executes that transfer as an actual memory cycle. if terminal count is generated in dma transfer cycle accessing the npb area or ram area directly connected to the cpu core, however, terminal count (dmtcon) from the dma controller synchronized with vbclk is resynchronized with busclk, and these pins are asserted for 1 busclk period. (3) dmactv3 to dmactv0 (input) these pins input an acknowledge signal (dmaack) from the internal dmac. (4) dmactvm3 to dmactvm0 (output) these pins output an acknowledge signal (dmaack) of the internal dmac cycle. these pins become active (high-level output) during dma flyby transfer. (5) dmxtco13 to dmxtco10 and dmxtco03 to dmxtco00 (input) these pins input a terminal count from the na85e300 (external dmac connected to the cpu core). (6) dmxtcm13 to dmxtcm10 and dmxtcm03 to dmxtcm00 (output) these pins output the terminal count of the na85e300 cycle. if the dma transfer cycle issued by the na85e300 is for transfer involving the terminal count (dmxtco1n, dmxtco0n), these pins output a high level during the first 1busclk period in which the NA85E535 executes the transfer as the first memory cycle (n = 3 to 0). if terminal count occurs in the dma transfer cycle accessing the npb area or ram area directly connected to the cpu core, these pins becomes active during 1busclk period immediately after the terminal count has been acknowledged, regardless of the memory cycle. (7) dmxcsz13 to dmxcsz10 and dmxcsz03 to dmxcsz00 (input) these pins input a chip select signal from the na85e300. (8) dmxczm13 to dmxczm10 and dmxczm03 to dmxczm00 (output) these pins output the chip select signal of the na85e300 cycle. these pins becomes active (low-level output) during dma flyby transfer.
chapter 2 pin functions preliminary user?s manual a15555ej2v0um 44 2.2.5 separate unit test mode pins (1) tbi9 to tbi4 (input) these pins input shift data for the separate unit test. (2) tbi3 (input) this pin inputs a reset signal for the separate unit test. (3) tbi2 (input) this pin inputs a clock for the separate unit test. (4) tbi1 (input) this pin inputs a chip select signal for the separate unit test. (5) tbi0 (input) this pin inputs an enable signal for the separate unit test. (6) tbo15 to tbo0 (output) these pins output shift data for the separate unit test. (7) bunri (input) this pin inputs the bunri signal for the separate unit test. (8) test (input) this pin inputs the test signal for the separate unit test. 2.2.6 pins reserved by nec (1) mpxen, phtest, phtdin1, phtdin0, and vptclk (input) this pin is reserved by nec. always input a low level to this pin. (2) vbresz and mwaitz (input) this pin is reserved by nec. always input a high level to this pin. (3) astbz, dstbz, mpxcz, phtdo1, and phtdo0 (output) these pins are reserved by nec. leave these pins open.
chapter 2 pin functions preliminary user?s manual a15555ej2v0um 45 2.3 connection of unused pins pin name i/o recommended connection vdcsz7 to vdcsz0, vsa25 to vsa0, vsbenz3 to vsbenz0, vsctyp2 to vsctyp0, vbdo31 to vbdo0, vpresz, vsseq2 to vsseq0, vswrite, vsstz, vaack, vpstb, vpubenz, vpa13 to vpa0, vpwrite, vpdw15 to vpdw0, vbclk input vbdi31 to vbdi0, vaexreq, vacbrrq, vswait, vsahld, vslast, vpretr, vpdr15 to vpdr0 output ? (be sure to use these pins.) vpdv, vmlock, stpak output leave these pins open. cpu core connection pins vbclk2, stprq input input a high level to this pin. mce input input a high level to this pin. ckmd1, ckmd0, v2en input input a low level to these pins. initialization pins lbs1, lbs0 input input a signal to these pins in accordance with the external bus setting. a25 to a0, do31 to do0, rdzr, rdzf, wrz3 to wrz0, wrstbz, iordzr, iordzf, iowrz, hldakz, dc3r to dc0r, dc3f to dc0f, csz7 to csz0, benz3 to benz0, bcystz, refrqz, busclk, busclk2, sdrasz, sdcasz, sdwez, cke, dqm3 to dqm0, wrstz, me7 to me0 output leave these pins open. di31 to di0, selfref input input a low level to these pins. external memory connection pins waitz, hldrqz input input a high level to these pins. dmtco3 to dmtco0, dmactv3 to dmactv0, dmxtco13 to dmxtco10, dmxtco03 to dmxtco00 input input a low level to these pins. dmxcsz13 to dmxcsz10, dmxcsz03 to dmxcsz00 input input a high level to these pins. dma pins dmtcom3 to dmtcom0, dmactvm3 to dmactvm0, dmxtcm13 to dmxtcm10, dmxtcm03 to dmxtcm00, dmxczm13 to dmxczm10, dmxczm03 to dmxczm00 output leave these pins open. tbi19 to tbi2 input input a low or high level to these pins. tbi1, tbi0 input input a high level to these pins. tbo15 to tbo0 output leave these pins open. separate unit test mode pins bunri, test input input a low level to these pins. mpxen, phtest, phtdin1, phtdin0, vptclk input input a low level to this pin. vbresz, mwaitz input input a high level to this pin. pins reserved by nec astbz, dstbz, mpxcz, phtdo1, phtdo0 output leave these pins open.
chapter 2 pin functions preliminary user?s manual a15555ej2v0um 46 2.4 pin status the following table shows the status of pins with an output function in each operation mode. table 2-8. pin status in each operation mode (1/2) pin status normal mode test mode pin name reset stop mode halt mode bus hold standby test mode note 1 unit test mode note 1 vbdi31 to vbdi0 0 0 operates note 2 0 undefined operates vaexreq 0 1 operates note 2 1 undefined operates vacbrrq 0 0 operates 0 undefined operates vmlock 0 1 operates 1 undefined operates vswait 0 0 operates note 2 0 undefined operates vsahld 0 0 operates note 2 0 undefined operates vslast 0 0 operates note 2 0 undefined operates vpretr 0 0 0 0 undefined operates vpdr15 to vpdr0 0 0 operates note 2 0 undefined operates vpdv 0 0 operates note 2 0 undefined operates cpu core connection pins stpak 0 1 operates 0 undefined operates a25 to a0 0 0 operates 0 undefined operates do31 to do0 0 held operates held undefined operates rdzr 1 1 operates 1 undefined operates rdzf 1 1 operates 1 undefined operates wrz3 to wrz0 1 1 operates 1 undefined operates wrstbz 1 1 operates 1 undefined operates iordzr 1 1 operates 1 undefined operates iordzf 1 1 operates 1 undefined operates iowrz 1 1 operates 1 undefined operates hldakz 1 1 operates 0 undefined operates dc3r to dc0r 1 1 operates 1 undefined operates dc3f to dc0f 1 0 operates 0 undefined operates csz7 to csz0 1 1 operates 1 undefined operates benz3 to benz0 1 1 operates 1 undefined operates bcystz 1 1 operates 1 undefined operates refrqz 1 0 operates operates undefined operates busclk note 3 0 operates operates undefined operates busclk2 note 4 0 operates operates undefined operates sdrasz 1 1 operates 1 undefined operates sdcasz 1 1 operates 1 undefined operates external memory connection pins sdwez 1 1 operates 1 undefined operates
chapter 2 pin functions preliminary user?s manual a15555ej2v0um 47 table 2-8. pin status in each operation mode (2/2) pin status normal mode test mode pin name reset stop mode halt mode bus hold standby test mode note 1 unit test mode note 1 cke 1 0 operates 1 undefined operates dqm3 to dqm0 1 1 operates 1 undefined operates wrstz 0 0 operates 0 undefined operates external memory connection pins me7 to me0 note 5 held operates held undefined operates dmtcom3 to dmtcom0 0 0 operates 0 undefined operates dmactvm3 to dmactvm0 0 0 operates 0 undefined operates dmxtcm13 to dmxtcm10, dmxtcm03 to dmxtcm00 0 0 operates 0 undefined operates dma pins dmxczm13 to dmxczm10, dmxczm03 to dmxczm00 1 1 operates 1 undefined operates cb-10vx hi-z hi-z hi-z hi-z hi-z operates separate unit test mode pins tbo15 to tbo0 cb-12m 0 0 0 0 0 operates notes 1. the standby test mode or unit test mode can be selected by the input levels of the bunri and test pins. test mode bunri pin input level test pin input level standby test mode high level low level unit test mode high level high level 2. if a refresh occurs in the halt mode and the NA85E535 is the bus master, the same value as in the stop mode is output. 3. if a low level (divided by one setting) is input to the ckmd1 and ckmd0 pins, the level input to the vbclk pin is output. in other cases, the operation is undefined until a vbclk signal of 1 clock or longer is input during the reset period (in which a low level is input to the vpresz pin). a low level is output when a vbclk signal of 1 clock or longer is input. 4. if a low level (divided by one setting) is input to the ckmd1 and ckmd0 pins, the level input to the vbclk2 pin is output. in other cases, the operation is undefined until a vbclk2 signal of 1 clock or longer is input during the reset period (in which a low level is input to the vpresz pin). a low level is output when a vbclk2 signal of 1 clock or longer is input. 5. when a low level is input to the mce pin: 0 when a high level is input to the mce pin: 1 remark 0: low-level output, 1: high-level output, hi-z: high impedance, operates: outputs valid signal
preliminary user?s manual a15555ej2v0um 48 chapter 3 bus control function 3.1 control registers the bus cycle function of the NA85E535 is specified by the operation mode setting pins and the control registers listed below. each control register is allocated to the peripheral i/o area of the cpu core. remark the setting of the control registers is invalid for rom connected to vfb (v850e fetch bus) of the cpu core or ram connected to vdb (v850e data bus). table 3-1. control register list (1/2) bit unit for manipulation address register name symbol r/w 1 bit 8 bits 16 bits default value fffff480h bus cycle type configuration register 0 bct0 r/w ?? 8888h/ 0000h fffff482h bus cycle type configuration register 1 bct1 r/w ?? 8888h/ 0000h fffff484h data wait control register 0 dwc0 r/w ?? 7777h fffff486h data wait control register 1 dwc1 r/w ?? 7777h fffff488h bus cycle control register bcc r/w ?? ffffh fffff48ah address setting wait control register asc r/w ?? ffffh fffff48ch flyby transfer strobe control register bcp r/w ?? 00h fffff48eh local bus sizing control register lbs r/w ?? 0000h/ 5555h/ aaaah fffff490h line buffer control register 0 lbc0 r/w ?? 0000h fffff492h line buffer control register 1 lbc1 r/w ?? 0000h fffff494h dma flyby transfer wait control register fwc r/w ?? 7777h fffff496h dma flyby transfer idle control register fic r/w ?? 3333h fffff498h bus mode control register bmc r/w ?? 00h/01h/ 02h/03h/ 80h/81h/ 82h/83h fffff49ah page rom configuration register prc r/w ?? 7000h fffff4a4h sdram configuration register 1 scr1 r/w ?? 30c0h fffff4a6h sdram refresh control register 1 rfs1 r/w ?? 0000h fffff4ach sdram configuration register 3 scr3 r/w ?? 30c0h fffff4aeh sdram refresh control register 3 rfs3 r/w ?? 0000h fffff4b0h sdram configuration register 4 scr4 r/w ?? 30c0h fffff4b2h sdram refresh control register 4 rfs4 r/w ?? 0000h fffff4b8h sdram configuration register 6 scr6 r/w ?? 30c0h
chapter 3 bus control function preliminary user?s manual a15555ej2v0um 49 table 3-1. control register list (2/2) bit unit for manipulation address register name symbol r/w 1 bit 8 bits 16 bits default value fffff4bah sdram refresh control register 6 rfs6 r/w ?? 0000h fffff4c4h setting register for mobileram expansion mode register 1 esc1 r/w ?? 0000h fffff4cch setting register for mobileram expansion mode register 3 esc3 r/w ?? 0000h fffff4d0h setting register for mobileram expansion mode register 4 esc4 r/w ?? 0000h fffff4d8h setting register for mobileram expansion mode register 6 esc6 r/w ?? 0000h
chapter 3 bus control function preliminary user?s manual a15555ej2v0um 50 3.1.1 bus cycle type configuration registers 0 and 1 (bct0 and bct1) the bct0 and bct1 registers enable operation of the NA85E535 in each csn area and specify the type of memory to be connected (n = 7 to 0). these registers can be read or written in 16-bit units. figure 3-1. bus cycle type configuration registers 0 and 1 (bct0 and bct1) 1514131211109876543210 bct0 me3 0 bt3 1 bt3 0 me2 0 bt2 1 bt2 0 me1 0 bt1 1 bt1 0 me0 0 bt0 1 bt0 0 address fffff480h default value note bct1 me7 0 bt7 1 bt7 0 me6 0 bt6 1 bt6 0 me5 0 bt5 1 bt5 0 me4 0 bt4 1 bt4 0 address fffff482h default value note bit position bit name meaning 15, 11, 7, 3 men enables or disables operation of NA85E535 in each csn area. 0: disabled (no response to cpu core) 1: enabled sets the type of memory to be connected for each csn area btn1 btn0 connected memory 0 0 sram (or external i/o) 0 1 page rom 1 0 setting prohibited 1 1 when n = 6, 4, 3, or 1: sdram when n = 7, 5, 2, or 0: setting prohibited 13, 12, 9, 8, 5, 4, 1, 0 btn1, btn0 note the default value differs as follows depending on the input level of the mce pin at reset. mce pin input level mpxen pin input level default value high level low level 8888h low level low level 0000h cautions 1. be sure to input a low level to the mpxen pin. 2. be sure to clear bits 14, 10, 6, and 2 to 0 (otherwise, the operation is not guaranteed). 3. set the bct0 and bct1 registers immediately after reset. do not change the set values of these registers (however, the men bit may be changed). remark n = 7 to 0
chapter 3 bus control function preliminary user?s manual a15555ej2v0um 51 3.1.2 address setting wait control register (asc) the asc register specifies the number of address setting wait states to be inserted at the beginning of the sram read/write cycle or page rom read cycle, for each csn area (n = 7 to 0). this register can be read or written in 16-bit units. remarks 1. the setting of this register is invalid when sdram is accessed. 2. the external wait function by the waitz pin is invalid during the address setting wait period. figure 3-2. address setting wait control register (asc) 1514131211109876543210 asc ac7 1 ac7 0 ac6 1 ac6 0 ac5 1 ac5 0 ac4 1 ac4 0 ac3 1 ac3 0 ac2 1 ac2 0 ac1 1 ac1 0 ac0 1 ac0 0 address fffff48ah default value ffffh bit position bit name meaning sets the number of address setting wait states for each csn area. acn1 acn0 number of address setting wait states 000 011 102 1 1 3 (default value) 15 to 0 acn1, acn0 remark n = 7 to 0
chapter 3 bus control function preliminary user?s manual a15555ej2v0um 52 3.1.3 bus cycle control register (bcc) the bcc register specifies the number of idle states to be inserted at the end of the sram read/write cycle, page rom read cycle, or sdram read cycle, for each csn area (n = 7 to 0). this register is used to make sure that the time required for the memory to release the external data bus elapses. the next bus cycle starts in the state following the idle states. the chip select signal (cszn) is not asserted in the idle states. this register can be read or written in 16-bit units. figure 3-3. bus cycle control register (bcc) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bcc bc7 1 bc7 0 bc6 1 bc6 0 bc5 1 bc5 0 bc4 1 bc4 0 bc3 1 bc3 0 bc2 1 bc2 0 bc1 1 bc1 0 bc0 1 bc0 0 address fffff488h default value ffffh bit position bit name meaning sets the number of idle states for each csn area. bcn1 bcn0 number of idle states 000 011 102 1 1 3 (default value) 15 to 0 bcn1, bcn0 remark n = 7 to 0
chapter 3 bus control function preliminary user?s manual a15555ej2v0um 53 3.1.4 flyby transfer strobe control register (bcp) the bcp register is used to specify the operations of the iordzr, iordzf, and iowrz signals during the read/write cycle when dma flyby transfer is not executed. when the ioen bit of this register is cleared to 0, the iordzr, iordzf, and iowrz signals do not operate during the read/write cycle when dma flyby transfer is not executed. when the ioen bit is set to 1, the iordzr, iordzf, and iowrz signals perform the same operations as the rdzr, rdzf, and wrstb signals, respectively, during the read/write cycle when dma flyby transfer is not executed. these signals operate, regardless of the value of the ioen bit, when dma flyby transfer is executed (the operation is the same). this register can be read or written in 8-bit units. figure 3-4. flyby transfer strobe control register (bcp) 76543210 bcp 0 0 0 0 ioen 0 0 0 address fffff48ch default value 00h bit position bit name meaning 3 ioen specifies operations of the iordzr, iordzf, and iowrz signals during the read/write cycle when dma flyby transfer is not executed. 0: does not operate. 1: operates. remark bits 7 to 4 and 2 to 0 are fixed to 0 (setting these bits to 1 is ignored).
chapter 3 bus control function preliminary user?s manual a15555ej2v0um 54 3.1.5 data wait control registers 0 and 1 (dwc0 and dwc1) the dwc0 and dwc1 registers specify the number of data wait cycle states to be inserted in the sram read/write cycle or page rom read cycle (off-page) for each csn area (n = 7 to 0). these registers can be read or written in 16-bit units. caution the number of wait states for the on-page cycle of page rom is set by the page rom configuration register (prc). figure 3-5. data wait control registers 0 and 1 (dwc0 and dwc1) 1514131211109876543210 dwc0 0 dw3 2 dw3 1 dw3 0 0 dw2 2 dw2 1 dw2 0 0 dw1 2 dw1 1 dw1 0 0 dw0 2 dw0 1 dw0 0 address fffff484h default value 7777h dwc1 0 dw7 2 dw7 1 dw7 0 0 dw6 2 dw6 1 dw6 0 0 dw5 2 dw5 1 dw5 0 0 dw4 2 dw4 1 dw4 0 address fffff486h default value 7777h bit position bit name meaning sets the number of wait states for each csn area. dwn2 dwn1 dwn0 number of wait states 0000 0011 0102 0113 1004 1015 1106 1 1 1 7 (default value) 14 to 12, 10 to 8, 6 to 4, 2 to 0 dwn2 to dwn0 remarks 1. n = 7 to 0 2. bits 15, 11, 7, and 3 are fixed to 0 (setting these bits to 1 is ignored).
chapter 3 bus control function preliminary user?s manual a15555ej2v0um 55 (1) external wait function when the NA85E535 is connected to a low-speed macro or an asynchronous system, wait states (external wait states) can be inserted in the bus cycle by using the external wait pin (waitz). the external wait states are inserted only in the data wait cycle. the external wait pin (waitz) is sampled at the rising edge of the busclk signal. (2) data wait control registers and external wait the number of wait states set by data wait control registers 0 and 1 (dwc0 and dwc1) is ored with the number of external wait states set by waitz input, and the resultant number of wait states is inserted. this means that the greater of the two values is inserted. wait by waitz input programmable wait wait control for example, three wait states are inserted in the bus cycle if the programmable wait and input to waitz pin occur at the following timing. waitz input wait by waitz input programmable wait wait control t1 tw tw tw t2 busclk
chapter 3 bus control function preliminary user?s manual a15555ej2v0um 56 3.1.6 page rom configuration register (prc) if a page rom sequential bus cycle is generated, the NA85E535 compares the current address with the address immediately after the generated page rom cycle to identify whether the access is on-page access. the prc register sets a width for address comparison and the number of wait states to be inserted in the on-page cycle. this register can be read or written in 16-bit units. caution the number of wait states to be inserted in the off-page cycle is set by the data wait control registers 0 and 1 (dwc0 and dwc1). figure 3-6. page rom configuration register (prc) 1514131211109876543210 prc 0 prw 2 prw 1 prw 0 00000000ma6ma5ma4ma3 address fffff49ah default value 7000h bit position bit name meaning sets the number of data wait states for on-page cycle of page rom. prw2 prw1 prw0 number of data wait states 0000 0011 0102 0113 1004 1015 1106 1 1 1 7 (default value) 14 to 12 prw2 to prw0 sets mask bits for address comparison. ma6 ma5 ma4 ma3 number of bits successively read 0 0 0 0 32 bits 2, 16 bits 4, 8 bits 8 (default value) 0 0 0 1 32 bits 4, 16 bits 8, 8 bits 16 0 0 1 1 32 bits 8, 16 bits 16, 8 bits 32 0 1 1 1 32 bits 16, 16 bits 32, 8 bits 64 1 1 1 1 32 bits 32, 16 bits 64, 8 bits 128 other than above setting prohibited (operation is not guaranteed if this setting is made.) 3 to 0 ma6 to ma3 remark bits 15 and 11 to 4 are fixed to 0 (setting these bits is ignored).
chapter 3 bus control function preliminary user?s manual a15555ej2v0um 57 an example of address mask control if four page roms of 1 mwords 8 bits are connected is illustrated below. figure 3-7. example of control by ma6 to ma3 bits a25 a21 a8 a6 a5 a4 a3 ma6 0 ma5 0 ma4 0 ma3 1 a25 a21 a8 a7 a6 a5 a4 a3 a2 a1 a0 a19 a6 a5 a4 a3 a2 a1 a0 comparison ? ? ? ? ? note off-page address on-page address internal address latch (address immediately before) page rom address prc register output address a7 note these bits are not used if the data bus width is 32 bits.
chapter 3 bus control function preliminary user?s manual a15555ej2v0um 58 3.1.7 sdram configuration register n (scrn) the scrn register sets the number of wait states for accessing sdram and an address multiplex width for each csn area (n = 6, 4, 3, or 1). if data is written to this register, the NA85E535 starts a register write operation. this register can be read or written in 16-bit units. cautions 1. the sdram read/write cycle is not generated before execution of the register write operation. read the value of the scrn register to check if the wcf bit is set to 1, before accessing sdram. 2. before writing data to the scrn register again after accessing sdram, be sure to clear the me bit of the bct0 and bct1 registers to 0 and then re-set to 1. 3. do not consecutively execute instructions that write data to the scrn registers. be sure to insert another instruction between the instructions that write data to the scrn register. 4. before accessing sdram, make sure that all settings of the scrn register are complete. remarks 1. n of the register name corresponds to a csn area number (n = 6, 4, 3, or 1). 2. be sure to clear bit 15 to 0. otherwise, the operation is not guaranteed. 3. bits 11 to 9 are fixed to 0 (setting these bits is ignored). figure 3-8. sdram configuration register n (scrn) (1/3) 1514131211109876543210 addressdefault value scrn 0 ltm 2 ltm 1 ltm 0 000wcf bcw 1 bcw 0 sso 1 sso 0 raw 1 raw 0 saw 1 saw 0 fffff4a0h +4n 30c0h bit position bit name meaning sets the value of cas latency during read. ltm2 ltm1 ltm0 cas latency 0 0 0 setting prohibited 0 0 1 1 (setting prohibited during dma flyby transfer) 0102 0 1 1 3 (default value) 1 any any setting prohibited 14 to 12 ltm2 to ltm0 8 wcf indicates that a register write command was completely executed to sdram after the scrn register was set. if the register write command is generated, this bit is set to 1. this bit can only be read. 0: setting not completed (default value) 1: setting completed remark n = 6, 4, 3, or 1
chapter 3 bus control function preliminary user?s manual a15555ej2v0um 59 figure 3-8. sdram configuration register n (scrn) (2/3) bit position bit name meaning sets the number of wait states from a bank active command to a read/write command, or from a precharge command to a bank active command. bcw1 bcw0 number of wait states 0 0 setting prohibited 011 102 1 1 3 (default value) 7, 6 bcw1, bcw0 sets the shift width of an address for identifying on-page access. if the data bus width is set to 16 or 32 bits, the system does not use the lower address (a0 or a1, a0). set these bits in accordance with the contents of the lbs register corresponding to the chip select area. sso1 sso0 address shift width 0 0 0 bit (data bus width: 8 bits) (default value) 01 1 bit (data bus width: 16 bits) note 10 2 bits (data bus width: 32 bits) note 1 1 setting prohibited 5, 4 sso1, sso0 sets a row address width. raw1 raw0 row address width 0 0 11 bits (default value) 01 12 bits note 10 13 bits note 1 1 setting prohibited 3, 2 raw1, raw0 sets an address multiplex width (column address width) for accessing sdram. saw1 saw0 address multiplex width (column address width) 0 0 8 bits (default value) 0 1 9 bits 10 10 bits note 11 11 bits note 1, 0 saw1, saw0 note refer to the next page for explanation.
chapter 3 bus control function preliminary user?s manual a15555ej2v0um 60 figure 3-8. sdram configuration register n (scrn) (3/3) note the following setting is prohibited because the upper limit of the address is exceeded. sso1 sso0 raw1 raw0 saw1 saw0 setting 0 1 1 0 1 1 data bus width: 16 bits row address width: 13 bits column address width: 11 bits 1 0 0 1 1 1 data bus width: 32 bits row address width: 12 bits column address width: 11 bits 1 0 1 0 1 0 data bus width: 32 bits row address width: 13 bits column address width: 10 bits 1 data bus width: 32 bits row address width: 13 bits column address width: 11 bits
chapter 3 bus control function preliminary user?s manual a15555ej2v0um 61 table 3-2. row address output bit setting address pin saw1 saw0 a25 to a18 a17 a16 a15 a14 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 0 0 a25 to a18 a25 a24 a23 a22 a21 a20 a19 a18 a17 a16 a15 a14 a13 a12 a11 a10 a9 a8 0 1 a25 to a18 a17 a25 a24 a23 a22 a21 a20 a19 a18 a17 a16 a15 a14 a13 a12 a11 a10 a9 1 0 a25 to a18 a17 a16 a25 a24 a23 a22 a21 a20 a19 a18 a17 a16 a15 a14 a13 a12 a11 a10 1 1 a25 to a18 a17 a16 a15 a25 a24 a23 a22 a21 a20 a19 a18 a17 a16 a15 a14 a13 a12 a11 table 3-3. column address output (a) for all bank precharge commands bit setting address pin sso1 sso0 a25 to a18 a17 a16 a15 a14 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 0 0 a25 to a18 a17 a16 a15 a14 a13 a12 a11 1 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 0 1 a25 to a18 a17 a16 a15 a14 a13 a12 1 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 1 0 a25 to a18 a17 a16 a15 a14 a13 1 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 (b) for register write command bit setting address pin sso1 sso0 a25 to a18 a17 a16 a15 a14 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 0 0 0 00000000000ltm2ltm1ltm00000 0 1 0 0000000000ltm2ltm1ltm000000 1 0 0 000000000ltm2ltm1ltm0000000 (c) for read/write command bit setting address pin sso1 sso0 a25 to a18 a17 a16 a15 a14 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 0 0 a25 to a18 a17 a16 a15 a14 a12 a11 a10 0 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 0 1 a25 to a18 a17 a16 a15 a14 a12 a11 0 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 1 0 a25 to a18 a17 a16 a15 a14 a12 0 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0
chapter 3 bus control function preliminary user?s manual a15555ej2v0um 62 3.1.8 sdram refresh control register n (rfsn) the NA85E535 can generate the sdram cbr refresh and self-refresh cycles. the rfsn register enables refresh and sets the refresh interval for each csn area (n = 6, 4, 3, or 1). this register can be read or written in 16-bit units. remark n of the register name corresponds to a csn area number (n = 6, 4, 3, or 1). figure 3-9. sdram refresh control register n (rfsn) (1/2) 1514131211109876543210 addressdefault value rfsnren00000 rcc 1 rcc 0 00 rin 5 rin 4 rin 3 rin 2 rin 1 rin 0 fffff4a2h +4n 0000h bit position bit name meaning enables refresh. ren refresh setting 0 disables refresh (default value). 1 enables refresh. 15 ren sets a source clock factor for the refresh interval counter. rcc1 rcc0 count source clock factor (cfac) 0 0 32 (default value) 0 1 128 1 0 256 1 1 setting prohibited 9, 8 rcc1, rcc0 remark refresh count clock (trcy) = cfac/ : operating clock (busclk) remarks 1. n = 6, 4, 3, or 1 2. bits 14 to 10, 7, and 6 are fixed to 0 (setting these bits is ignored).
chapter 3 bus control function preliminary user?s manual a15555ej2v0um 63 figure 3-9. sdram refresh control register n (rfsn) (2/2) bit position bit name meaning sets a refresh interval factor. rin5 rin4 rin3 rin2 rin1 rin0 interval factor (ifac) 0000001 (default value) 0000012 0000103 0000114 ::::::: 11111164 5 to 0 rin5 to rin0 caution to change the setting of the rfsn register, follow these steps (n = 6, 4, 3, or 1). <1> clear the men bit of the bct register to 0. <2> clear the ren bit to 0. <3> set the men bit of the bct register to 1. <4> set a new value to the rcc1, rcc0, and rin5 to rin0 bits, and set the ren bit to 1. to change the refresh interval, set a value that allows refresh to be performed in time even when the interval is changed. table 3-4. example of sdram refresh interval interval factor (ifac)note default refresh interval ( s) refresh count clock (trcy) = 20 mhz = 33 mhz = 50 mhz = 66 mhz 32/ 9 (14.4) 16 (15.5) 24 (15.4) 32 (15.5) 128/ 2 (12.8) 4 (15.5) 6 (15.4) 8 (15.5) 15.6 256/ 1 (12.8) 2 (15.5) 3 (15.4) 4 (15.5) note ( ): calculated refresh interval ( s) refresh interval ( s) = trcy ifac remark : operating clock (busclk)
chapter 3 bus control function preliminary user?s manual a15555ej2v0um 64 3.1.9 setting register for mobileram expansion mode register n (escn) the escn register sets the mobileram operation for each csn area (n = 6, 4, 3, or 1). this register can be read or written in 16-bit units. cautions 1. the escn register does not have to be set when mobileram is not connected. 2. be sure to set the escn register before setting the scrn register. 3. be sure to re-set the escn and scrn registers and start a register write operation after the deep power down mode has been released. remark n of the register name corresponds to a csn area number (n = 6, 4, 3, or 1). figure 3-10. setting register for mobileram expansion mode register n (escn) (1/2) 1514131211109876543210 addressdefault value escn ers dpd 0 emb 12 emb 11 emb 10 emb 9 emb 8 emb 7 emb 6 emb 5 emb 4 emb 3 emb 2 emb 1 emb 0 fffff4c0h +4n 0000h bit position bit name meaning 15 ers specifies a write operation to the expansion mode register of mobileram during a register write operation. 0: does not write to the expansion mode register (default value). 1: writes to the expansion mode register. 14 dpd specifies the operation mode of mobileram when the cpu core enters the stop mode or when a high level is input to the selfref pin. 0: self-refresh cycle m ode (default value) note 1: deep power down mode 12 to 7 emb12 to emb7 specifies the expansion mode register (bits 12 to 7) of mobileram (default value: 0). set these bits in accordance with the specifications of the mobileram connected. note when the dpd bits of any of the escn registers is set to 1, even if the dpd bit of other registers is cleared to 0, the operation is changed to the deep power down mode. to operate mobileram in the self-refresh mode, therefore, clear the dpd bit of all the escn registers to 0. remarks 1. n = 6, 4, 3, or 1 2. bit 13 is fixed to 0 (setting this bit is ignored).
chapter 3 bus control function preliminary user?s manual a15555ej2v0um 65 figure 3-10. setting register for mobileram expansion mode register n (escn) (2/2) bit position bit name meaning sets bits 6 and 5 of the expansion mode register of mobileram. set these bits in accordance with the specifications of mobileram connected. set these bits as follows when mobileram of elpida memory. emb6 emb5 drive strength 0 0 normal (default value) 0 1 1/2 strength 1 0 1/4 strength 11reserved 6, 5 emb6, emb5 sets bits 4 and 3 of the expansion mode register of mobileram. set these bits in accordance with the specifications of mobileram connected. set these bits as follows when mobileram of elpida memory. emb4 emb3 self-refresh guarantee temperature 0070 c (default value) 0145 c 1015 c 1185 c 4, 3 emb4, emb3 sets bits 2 to 0 of the expansion mode register of mobileram. set these bits in accordance with the specifications of mobileram connected. set these bits as follows when mobileram of elpida memory. emb2 emb1 emb0 self-refresh operation area 0 0 0 all banks (default value) 0 0 1 bank a & bank b 0 1 0 bank a 0 1 1 reserved 1 0 0 reserved 1 0 1 1/2 of bank a 1 1 0 1/4 of bank b 1 1 1 reserved 2 to 0 emb2 to emb0
chapter 3 bus control function preliminary user?s manual a15555ej2v0um 66 the following figure shows a flow from setting the escn and scrn registers to completion of a register write operation. figure 3-11. flow from setting escn and scrn register to register write operation set escn register (when mobileram is connected). yes escn.ers = 1? no set scrn register. start register write operation. all bank precharge command refresh command ( 8) set mode register. set expansion mode register. end of register write operation (access enabled) register write operation all bank precharge command refresh command ( 8) set mode register. remark n = 6, 4, 3, or 1
chapter 3 bus control function preliminary user?s manual a15555ej2v0um 67 3.1.10 line buffer control registers 0 and 1 (lbc0 and lbc1) the NA85E535 includes a read buffer. the lbc0 and lbc1 registers set the operation conditions of the read buffer included in the NA85E535 for each csn area (n = 7 to 0). these registers can be read or written in 16-bit units. figure 3-12. line buffer control registers 0 and 1 (lbc0 and lbc1) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 lbc0 0 0 rb 31 rb 30 00 rb 21 rb 20 00 rb 11 rb 10 00 rb 01 rb 00 address fffff490h default value 0000h lbc1 0 0 rb 71 rb 70 00 rb 61 rb 60 00 rb 51 rb 50 00 rb 41 rb 40 address fffff492h default value 0000h bit position bit name meaning sets the operating conditions (timing to execute speculative read) of the read buffer for each csn area. rbn1 rbn0 timing of speculative read 0 0 no speculative read (operation of read buffer prohibited) (default value) 0 1 no speculative read (operation of read buffer prohibited) 1 0 in dma/fetch cycle 1 1 in all cycles 13, 12, 9, 8, 5, 4, 1, 0 rbn1, rbn0 remarks 1. n = 7 to 0 2. be sure to clear bits 15, 11, 7, and 3 to 0. otherwise, the operation is not guaranteed. 3. bits 14, 10, 6, and 2 are fixed to 0 (setting these bits is ignored). 4. if the setting of the rbn1 and rbn0 bits is changed, the data retained in the read buffer becomes invalid immediately after changing. the read buffer has a capacity of 4 words (128 bits) and enables execution of speculative read operations. the speculative read range is the addresses (xxxxxx0h to xxxxxxfh) on the same line as the address that has been accessed (critical first access method). for example, addresses ?xxxxx00h?, ?xxxxx04h?, and ?xxxxx01h? are accessed in the following sequence, and data is loaded to the read buffer (when speculative read is executed with the local bus size of 32 bits). ? when accessing address ?xxxxx00h?: xxxxx00h xxxxx04h xxxxx08h xxxxx0ch ? when accessing address ?xxxxx04h?: xxxxx04h xxxxx08h xxxxx0ch xxxxx00h ? when accessing address ?xxxxx01h?: xxxxx01h xxxxx05h xxxxx09h xxxxx0dh the NA85E535 has an internal buffer of four stages (128 bits) and, if a write request is generated while the buffer is full, outputs a wait response until a vacancy is available in the buffer.
chapter 3 bus control function preliminary user?s manual a15555ej2v0um 68 (1) recommended setting of speculative read function the following explanation shows the cases indicating whether or not speculative read should be set for an individual memory type. note, however, that the following explanation only indicates whether the probability that speculative read improves the performance is high or low, and does not guarantee that the performance is improved. whether speculative read is actually executed or not must be determined based on the access condition of the system and the set value of each wait cycle. (a) sram ? case where speculative read should be set ? 2-cycle transfer by using the dma controller with on-chip cpu core note ? dma 2-cycle transfer when using the na85e300 ? case where speculative read should not be set ? random data access by cpu ? fetch access ? transfer involving sequential status (cache refill) note especially when performing line transfer and setting wait, setting speculative read is advantageous. (b) page rom/sdram ? case where speculative read should be set ? 2-cycle transfer by using the dma controller with on-chip cpu core note 1 ? dma 2-cycle transfer when using the na85e300 ? fetch access note 2 (when setting address setup wait/idle wait) ? case where speculative read should not be set ? random data access by cpu ? transfer involving sequential status note 3 (cache refill) notes 1. especially when performing line transfer and setting wait, setting speculative read is advantageous. 2. depending on the branch rate of the program to be fetched, speculative read should not be set. 3. if a sequential access occurs from vsb, there is no problem if speculative read is set because the NA85E535 gives priority to the request from vsb.
chapter 3 bus control function preliminary user?s manual a15555ej2v0um 69 3.1.11 bus mode control register (bmc) the bmc register is used to select the vsb specifications and set the rate by which the vbclk/vbclk2 signal is to be divided. the divided vbclk/vbclk2 signal is output from the busclk/busclk2 pin as the bus clock. the divided busclk signal is also used as an internal system clock. when the bmc register is written, an npb write retry cycle is always generated, and the busclk/busclk2 signal stops once for the duration of 12 clocks of the vbclk/vbclk2 signal. the busclk/busclk2 signal resumes its operation with the divided clock set after it had stopped. while the busclk/busclk2 signal is stopped, the sdram refresh control register (rfsn) of sdram also stops operating. therefore, re-set the refresh cycle before setting the bmc register so that refresh occurs correctly within the refresh interval required by the sdram to be connected (n = 6, 4, 3, or 1). if the power-saving mode is selected by setting the pdwn bit to 1, the internal system clock is stopped, and all the internal registers are initialized. this register can be read or written in 8-bit units. cautions 1. immediately before setting the pdwn bit to 1, be sure to clear (0) all the men bits of bus cycle type configuration registers 0 and 1 (bct1 and bct0) to 0 (clear the men bits to 0 and set the pdwn bit to 1 successively) (n = 7 to 0). the operation is not guaranteed if another bus cycle occurs between clearing the men bits to 0 and setting the pdwn bit to 1. for the setting procedure, refer to figure 3-14 (the operation is not guaranteed if the setting is made in a way other than the procedure shown in figure 3-14). 2. when the pdwn bit is set to 1, all the internal settings of the NA85E535 are initialized. to change the division ratio of the internal system clock set by the ckmd1 and ckmd0 pins by using the ckm1 and ckm0 bits, set the normal operation mode (by clearing the pdwn bit to 0) and then set the ckm1 and ckm0 bits again. for the setting procedure, refer to figure 3-15 (the operation is not guaranteed if the setting is made in a way other than the procedure shown in figure 3-15). when using the division ratio of the internal system clock by changing the setting of the ckm1 and ckm0 bits, a clock whose frequency is different from the set division ratio is output if the pwdn bit is set to 1 (a glitch is generated on the busclk/busclk2 signal). therefore, the external circuit using the busclk/busclk2 signal must be initialized, depending on whether the pdwn bit is set to 1. 3. change the division ratio by changing the setting of the ckm1 and ckm0 bits in the procedure shown in figure 3-16 (the operation is not guaranteed if the setting is made in a way other than the procedure shown in figure 3-16). in this case, an npb write retry cycle may be repeatedly issued until the phase relationship of the clock is stabilized.
chapter 3 bus control function preliminary user?s manual a15555ej2v0um 70 figure 3-13. bus mode control register (bmc) 76543210 bmcv2en0000pdwnckm1ckm0 address fffff498h default value note bit position bit name meaning 7 v2en selects the specification of the vsb that connects the NA85E535. set this bit in accordance with the cpu core to be used. if a cpu core covered by this manual is used, input a low level to this bit. 0: conforms to vsb specifications. 1: conforms to vsb2 specifications (support of bus reset, disconnect response, and busy response). 2 pdwn selects an operation mode of the NA85E535. when this bit is set to 1, the internal system clock stops. 0: normal operation mode (default value) 1: power-saving mode (operation stops.) sets the division ratio by which the vbclk/vbclk2 signal is to be divided to generate the bus clock (busclk/busclk2). divided busclk signal is used as an internal system clock. ckm1 ckm0 division ratio of vbclk/vbclk2 signal to generate busclk/busclk2 signal 0 0 1/1 (vbclk/vbclk2 is divided by 1.) 0 1 1/2 (vbclk/vbclk2 is divided by 2.) 1 0 1/3 (vbclk/vbclk2 is divided by 3.) 1 1 1/4 (vbclk/vbclk2 is divided by 4.) 1, 0 ckm1, ckm0 note the default value differs as follows, depending on the input levels of the v2en, ckmd1, and ckmd0 pins at reset. v2en pin input level ckmd1 pin input level ckmd0 pin input level default value high level 83h high level low level 82h high level 81h high level low level low level 80h high level 03h high level low level 02h high level 01h low level low level low level 00h remark bits 6 to 3 are fixed to 0 (setting these bits is ignored).
chapter 3 bus control function preliminary user?s manual a15555ej2v0um 71 figure 3-14. procedure of setting pdwn bit (1) clear all me7 to me0 bits of bct0 and bct1 registers. set pdwn bit of bmc register to 1. stop internal clock of NA85E535 and busclk/busclk2 signal. (glitch is generated on busclk/busclk2 signal when it is stopped.) (do not allow other bus cycles to occur during this time.) initialize internal circuit. figure 3-15. procedure of clearing pdwn bit (0) stop internal clock of NA85E535 and busclk/busclk2 signal. (slave (circuit) using busclk/busclk2 signal must be initialized.) initialize internal circuit. clear pdwn bit of bmc register to 0. (ckm1 and ckm0 bits of bmc register are automatically set to default value.) if division ratio other than default value is used, set ckm1 and ckm0 bits of bmc register (refer to figure 3-17 ). set each control register.
chapter 3 bus control function preliminary user?s manual a15555ej2v0um 72 figure 3-16. procedure of setting ckm1 and ckm0 bits save set value of npb strobe wait control register (vswc). set all vswln bits of vswc register to 1. (target cpu core: n = 2 to 0/nx85e2x (under development): n = 3 to 0) set ckm1 and ckm0 bits of bmc register. restore set value of vswc register saved. (busclk/busclk2 signal stops once during this time.)
chapter 3 bus control function preliminary user?s manual a15555ej2v0um 73 3.1.12 local bus sizing control register (lbs) the lbs register sets the data bus width of the memory to be accessed, for each csn area (n = 7 to 0). this register can be read or written in 16-bit units. figure 3-17. local bus sizing control register (lbs) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 lbs lb 71 lb 70 lb 61 lb 60 lb 51 lb 50 lb 41 lb 40 lb 31 lb 30 lb 21 lb 20 lb 11 lb 10 lb 01 lb 00 address fffff48eh default value note 1 bit position bit name meaning sets the data bus width of the connected memory for each csn area. lbn1 lbn0 data bus width maximum number of times of successive transfer note 2 0 0 8 bits 32 times (vsseq2 to vsseq0 = 1, 0, 1) 0 1 16 bits 64 times (vsseq2 to vsseq0 = 1, 1, 0) 1 any 32 bits 128 times (vsseq2 to vsseq0 = 1, 1, 1) 15 to 0 lbn1, lbn0 notes 1. the default value differs as follows depending on the input levels of the lbs1 and lbs0 pins reset. lbs1 pin input level lbs0 pin input level default value low level low level aaaah low level high level 5555h high level any 0000h 2. the maximum number of times of successive transfer vsb can request from the NA85E535 differs depending on the data bus width setting (specify the maximum number of times of successive transfer by using vsseq2 to vsseq0, and do not input a value other than the above). successive transfers exceeding a page of sdram are prohibited. remark n = 7 to 0
chapter 3 bus control function preliminary user?s manual a15555ej2v0um 74 3.1.13 dma flyby transfer wait control register (fwc) the fwc register sets the number of data wait states for channel n (n = 3 to 0) during dma flyby transfer. the set value of this register is valid during dma flyby transfer, and the set values of the dwc0, dwc1, and prc registers are invalid. this register can be read or written in 16-bit units. figure 3-18. dma flyby transfer wait control register (fwc) 1514131211109876543210 fwc 0 fw 32 fw 31 fw 30 0 fw 22 fw 21 fw 20 0 fw 12 fw 11 fw 10 0 fw 02 fw 01 fw 00 address fffff494h default value 7777h bit position bit name meaning sets the number of data wait states for dma flyby transfer for channel n. fwn2 fwn1 fwn0 number of data wait states 0000 0011 0102 0113 1004 1015 1106 1 1 1 7 (default value) 14 to 12, 10 to 8, 6 to 4, 2 to 0 fwn2 to fwn0 remarks 1. n = 3 to 0 2. bits 15, 11, 7, and 3 are fixed to 0 (setting these bits is ignored).
chapter 3 bus control function preliminary user?s manual a15555ej2v0um 75 3.1.14 dma flyby transfer idle control register (fic) the fic register sets the number of idle states for channel n (n = 3 to 0) during dma flyby transfer. the set value of this register is valid during dma flyby transfer, and the set value of the bcc register is invalid. this register can be read or written in 16-bit units. figure 3-19. dma flyby transfer idle control register (fic) 1514131211109876543210 fic 0 0 fi 31 fi 30 00 fi 21 fi 20 00 fi 11 fi 10 00 fi 01 fi 00 address fffff496h default value 3333h bit position bit name meaning sets the number of idle states for dma flyby transfer for channel n. fin1 fin0 number of idle states 000 011 102 1 1 3 (default value) 13, 12, 9, 8, 5, 4, 1, 0 fin1, fin0 remarks 1. n = 3 to 0 2. bits 15, 14, 11, 10, 7, 6, 3, and 2 are fixed to 0 (setting these bits is ignored).
chapter 3 bus control function preliminary user?s manual a15555ej2v0um 76 3.2 examples of memory connection 3.2.1 example of sram connection figure 3-20. sram connection example 1 a18 to a2 di31 to di24 csz rdzf wrz3 NA85E535 di23 to di16 wrz2 di15 to di8 wrz1 di7 to di0 wrz0 do31 to do24 do23 to do16 do7 to do0 do15 to do8 a16 to a0 cs we oe i/o8 to i/o1 dc3f a16 to a0 cs we oe i/o8 to i/o1 dc2r a16 to a0 i/o8 to i/o1 a16 to a0 i/o8 to i/o1 i/o buffer rdzr dc3r dc2f cs we oe dc1r dc1f cs we oe dc0r dc0f sram (128 kwords 8 bits) sram (128 kwords 8 bits) sram (128 kwords 8 bits) i/o buffer i/o buffer i/o buffer sram (128 kwords 8 bits)
chapter 3 bus control function preliminary user?s manual a15555ej2v0um 77 figure 3-21. sram connection example 2 a18 to a1 di31 to di16 csz rdzf wrstbz NA85E535 do31 to do16 a17 to a0 cs we i/o16 to i/o1 sram (256 kwords 16 bits) dc2f oe hb lb benz2 benz3 a17 to a0 cs we i/o16 to i/o1 oe hb lb di15 to di0 do15 to do0 i/o buffer dc0f benz0 benz1 dc3r dc1r rdzr dc3f dc2r dc1f dc0r sram (256 kwords 16 bits) i/o buffer
chapter 3 bus control function preliminary user?s manual a15555ej2v0um 78 3.2.2 example of page rom connection figure 3-22. page rom connection example 1 (data bus width: 16 bits) a21 to a2 csz di15 to di0 page rom (1 mwords 16 bits) a19 to a0 ce oe o15 to o0 NA85E535 di31 to di16 i/o buffer dc1r dc0r dc3r rdzf rdzr dc3f dc2r dc2f a19 to a0 ce oe o15 to o0 dc1f dc0f i/o buffer page rom (1 mwords 16 bits)
chapter 3 bus control function preliminary user?s manual a15555ej2v0um 79 figure 3-23. page rom connection example 2 (data bus width: 8 bits) NA85E535 a22 to a2 csz di7 to di0 page rom (2 mwords 8 bits) a20 to a0 o7 to o0 di15 to di8 di23 to di16 di31 to di24 oe i/o buffer dc3r rdzf rdzr ce dc3f a20 to a0 o7 to o0 oe ce dc2r dc2f a20 to a0 o7 to o0 oe ce dc1r dc1f a20 to a0 o7 to o0 oe ce dc0r dc0f i/o buffer i/o buffer i/o buffer page rom (2 mwords 8 bits) page rom (2 mwords 8 bits) page rom (2 mwords 8 bits)
chapter 3 bus control function preliminary user?s manual a15555ej2v0um 80 3.2.3 example of sdram connection figure 3-24. example of 64mb sdram connection NA85E535 sdram (1 mwords 16 bits 4) a11 to a0 dq15 to dq0 clk a13, a12 cke cs ras cas hdqm we a13 to a2 a23, a22 busclk csz sdrasz cke sdcasz sdwez dqm0 a11 to a0 clk a13, a12 cke cs ras cas ldqm we dqm3 di31 to di16 do31 to do16 dc2f i/o buffer dc3r dc3f dc2r di15 to di0 do15 to do0 dc0f dc1r dc1f dc0r dq15 to dq0 ldqm dqm2 dqm1 hdqm i/o buffer sdram (1 mwords 16 bits 4)
chapter 3 bus control function preliminary user?s manual a15555ej2v0um 81 (1) output of each address and connection of sdram the setting of sdram configuration register n (scrn) for each data bus width (8 bits, 16 bits, and 32 bits), physical address, address output from the NA85E535, and connection of sdram to the NA85E535 are explained below. (a) with data bus width of 8 bits here is an example of connecting 64 mb sdram (2 mwords 8 bits 4 banks) when the data bus width is 8 bits: ? setting of scrn register sso1, sso0 = 00: data bus width = 8 bits raw1, raw0 = 01: row address width = 12 bits saw1, saw0 = 01: column address width = 9 bits ? physical address a22, a21: bank address a20 to a9: row address a8 to a0: column address ? address output from NA85E535 a22, a21: bank address a11 to a0: row address (12 bits), column address (9 bits) row address and bank address output with active command row address a25 a24 a25 a24 a23 a22 a21 a20 a19 a18 a17 a25 a24 a23 a22 a21 a20 a19 a23 a22 a21 a20 a19 a18 a17 a16 a15 a14 a13 a12 a11 a10 a18 a17 a16 a15 a14 a13 a12 a11 a10 a9 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 bank address column address output with read/write command column address a25 a24 a25 a24 a23 a22 a21 a20 a19 a18 a17 a16 a15 a14 a12 a11 a10 0 a23 a22 a21 a20 a19 a18 a17 a16 a15 a14 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 ? connection of sdram to NA85E535 a22, a1 (NA85E535) ba0 (a13), ba1 (a12) (sdram) a11 to a0 (NA85E535) a11 to a0 (sdram)
chapter 3 bus control function preliminary user?s manual a15555ej2v0um 82 (b) with data bus width of 16 bits here is an example of connecting 512 mb sdram (8 mwords 16 bits 4 banks) when the data bus width is 16 bits: ? setting of scrn register sso1, sso0 = 01: data bus width = 16 bits raw1, raw0 = 10: row address width = 13 bits saw1, saw0 = 10: column address width = 10 bits ? physical address a25, a24: bank address a23 to a11: row address a10 to a1: column address ? address output from NA85E535 a25, a24: bank address a13 to a1: row address (13 bits), column address (10 bits) row address and bank address output with active command row address a25 a24 a25 a24 a23 a22 a21 a20 a19 a18 a17 a16 a25 a24 a23 a22 a21 a20 a23 a22 a21 a20 a19 a18 a17 a16 a15 a14 a13 a12 a11 a10 a19 a18 a17 a16 a15 a14 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 bank address column address output with active command column address a25 a24 a25 a24 a23 a22 a21 a20 a19 a18 a17 a16 a15 a14 a12 a11 0 a10 a23 a22 a21 a20 a19 a18 a17 a16 a15 a14 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 ? connection of sdram to NA85E535 a25, a24 (NA85E535) ba0 (a14), ba1 (a13) (sdram) a13 to a1 (NA85E535) a12 to a0 (sdram)
chapter 3 bus control function preliminary user?s manual a15555ej2v0um 83 (c) with data bus width of 32 bits here is an example of connecting 512 mb sdram (256 mb sdram (4 mwords 16 bits 4 banks) 2) when the data bus width is 32 bits: ? setting of scrn register sso1, sso0 = 10: data bus width = 32 bits raw1, raw0 = 10: row address width = 13 bits saw1, saw0 = 01: column address width = 9 bits ? physical address a25, a24: bank address a23 to a11: row address a10 to a2: column address ? address output from NA85E535 a25, a24: bank address a14 to a2: row address (13 bits), column address (9 bits) row address and bank address output with active command row address a25 a24 a25 a24 a23 a22 a21 a20 a19 a18 a17 a25 a24 a23 a22 a21 a20 a19 a23 a22 a21 a20 a19 a18 a17 a16 a15 a14 a13 a12 a11 a10 a18 a17 a16 a15 a14 a13 a12 a11 a10 a9 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 bank address column address output with active command column address a25 a24 a25 a24 a23 a22 a21 a20 a19 a18 a17 a16 a15 a14 a12 0 a11 a10 a23 a22 a21 a20 a19 a18 a17 a16 a15 a14 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 ? connection of sdram to NA85E535 a25, a4 (NA85E535) ba0 (a14), ba1 (a13) (sdram) a14 to a2 (NA85E535) a12 to a0 (sdram)
chapter 3 bus control function preliminary user?s manual a15555ej2v0um 84 (2) bank address output the NA85E535 precharges the bank it is about to access when it outputs a row address immediately after page change as a bank precharge command. after bank change, the NA85E535 also precharges the bank previously accessed when it outputs a column address. therefore, the bank is precharged both when a row address is output and when a column address is output. for this reason, always connect the pins of NA85E535 that output a bank address (a22 and a21) to the bank address pins (a13 and a12) of sdram when sdram is connected as explained in 3.2.3 (1) (a) with data bus width of 8 bits . an example of address output when the bank precharge command is executed to change the page and bank with the connection introduced in 3.2.3 (1) (a) with data bus width of 8 bits is shown below. (a) to change page (with data bus width of 8 bits) because the bank to be accessed is precharged, the physical addresses (a25 to a9) are output from the a25 to a0 pins of the NA85E535. row address a25 a24 a25 a24 a23 a22 a21 a20 a19 a18 a17 a25 a24 a23 a22 a21 a20 0 a23 a22 a21 a20 a19 a18 a17 a16 a15 a14 a13 a12 a11 a10 a18 a17 a16 a15 a14 a13 a12 a11 a10 a9 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 bank address to be accessed (b) to change bank (with data bus width of 8 bits) because the bank previously accessed is precharged, the physical addresses previously accessed (a25 to a9) are output from the a25 to a9 pins of the NA85E535. column address a25 a24 a25 a24 a23 a22 a21 a20 a19 a18 a17 a16 a15 a14 a12 a11 a10 0 a23 a22 a21 a20 a19 a18 a17 a16 a15 a14 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 bank address previously accessed the bits that determine the precharge mode (a10: 8-bit data bus width, a11: 16-bit data bus width, a12: 32-bit data bus width) output a high level when the all-bank precharge command is executed, and a low level when any other precharge command is executed.
chapter 3 bus control function preliminary user?s manual a15555ej2v0um 85 3.3 stop function when the cpu core enters the stop mode, the NA85E535 operates in the following sequence (refer to figure 3- 25 ). <1> when hardware stop or software stop instruction is executed, the cpu core inputs the stop mode request signal (stprq) to the NA85E535. <2> the NA85E535 outputs the vsb mastership request signal (vaexreq) to the cpu core. <3> the cpu core inputs an acknowledge signal (vaack) to the NA85E535 in response to the vareq signal. <4> if there is a csn area set as sdram, the all bank precharge command, nop command, and self-refresh command are output. <5> the NA85E535 returns an acknowledge signal (stpak) to the cpu core in response to the stprq signal. the NA85E535 returns the stpak signal two clocks, at the earliest, after it has received the stprq signal. if sdram is connected, the NA85E535 enters the stop status when the refrqz signal and cke signal go low. figure 3-25. operation of NA85E535 in stop mode cpu core NA85E535 vaexreq vaack <2> <3> vareq vaack stprq stpak <1> <5> stprq stpak <4> sdram sdrasz sdrasz <4> cszn cs <4> sdcasz sdcasz <4> sdwez sdwez <4> cke cke remark n = 6, 4, 3, or 1
chapter 3 bus control function preliminary user?s manual a15555ej2v0um 86 when releasing the stop mode, the NA85E535 operates in the following sequence (refer to figure 3-26 ). <1> the stop mode request signal (stprq) from the cpu core is cleared. <2> after the stprq has been cleared, the NA85E535 clears its acknowledge signal (stpak) in response to the stprq signal at the next rising edge of vbclk. <3> if there is a csn area that is set as sdram, a nop command is output and an idle state (bcw wait 4 busclk clocks) is inserted (n = 6, 4, 3, or 1). <4> the vsb mastership request signal (vaexreq) is cleared. <5> the acknowledge signal (vaack) from the cpu core in response to the vaexreq signal is cleared. if sdram is not set, <3> is not executed (for details, refer to figure 4-23 sdram self-refresh timing (stop timing) ). figure 3-26. operation of NA85E535 when stop mode is released cpu core NA85E535 vaexreq vaack <4> <5> vareq vaack stprq stpak <1> <2> stprq stpak <3> sdram cszn cs remark n = 6, 4, 3, or 1 (2) timing of setting/releasing stop mode figure 3-27 shows the timing of setting and releasing the stop mode. remark for details of the vsb signals, refer to nu85e hardware user?s manual (a14874e) .
chapter 3 bus control function preliminary user?s manual a15555ej2v0um 87 figure 3-27. timing of setting/releasing stop mode (without sdram setting) (1/4) (a) division by 1 vaack (input) vbclk (input) rdzf, rdzr (output) vbdo31 to vbdo0 (input) vmlock (output) refrqz (output) stpak (output) a25 to a0 (output) cke (output) vaexreq (output) vdcsz7 to vdcsz0 (input) dc3r to dc0r (output) vbdi31 to vbdi0 (output) stprq (input) wrz3 to wrz0 (output) csz7 to csz0 (output) sdrasz (output) sdcasz (output) sdwez (output) dqm3 to dqm0 (output) dc3f to dc0f (output) h l l h l h h h h h h h h h l busclk (output)
chapter 3 bus control function preliminary user?s manual a15555ej2v0um 88 figure 3-27. timing of setting/releasing stop mode (without sdram setting) (2/4) (b) division by 2 vaack (input) vbclk (input) rdzf, rdzr (output) vbdo31 to vbdo0 (input) vmlock (output) refrqz (output) stpak (output) a25 to a0 (output) cke (output) vaexreq (output) vdcsz7 to vdcsz0 (input) dc3r to dc0r (output) vbdi31 to vbdi0 (output) stprq (input) wrz3 to wrz0 (output) busclk (output) csz7 to csz0 (output) sdrasz (output) sdcasz (output) sdwez (output) dqm3 to dqm0 (output) dc3f to dc0f (output) h l l h l h h h h h h h h h l
chapter 3 bus control function preliminary user?s manual a15555ej2v0um 89 figure 3-27. timing of setting/releasing stop mode (without sdram setting) (3/4) (c) division by 3 vaack (input) vbclk (input) rdzf, rdzr (output) vbdo31 to vbdo0 (input) vmlock (output) refrqz (output) stpak (output) a25 to a0 (output) cke (output) vaexreq (output) vdcsz7 to vdcsz0 (input) dc3r to dc0r (output) vbdi31 to vbdi0 (output) stprq (input) wrz3 to wrz0 (output) busclk (output) csz7 to csz0 (output) sdrasz (output) sdcasz (output) sdwez (output) dqm3 to dqm0 (output) dc3f to dc0f (output) h l l h l h h h h h h h h h l
chapter 3 bus control function preliminary user?s manual a15555ej2v0um 90 figure 3-27. timing of setting/releasing stop mode (without sdram setting) (4/4) (d) division by 4 vaack (input) vbclk (input) rdzf, rdzr (output) vbdo31 to vbdo0 (input) vmlock (output) refrqz (output) stpak (output) a25 to a0 (output) cke (output) vaexreq (output) vdcsz7 to vdcsz0 (input) dc3r to dc0r (output) vbdi31 to vbdi0 (output) stprq (input) wrz3 to wrz0 (output) busclk (output) csz7 to csz0 (output) sdrasz (output) sdcasz (output) sdwez (output) dqm3 to dqm0 (output) dc3f to dc0f (output) h l l h l h h h h h h h h h l
chapter 3 bus control function preliminary user?s manual a15555ej2v0um 91 3.4 bus hold function when the hldrqz signal is asserted, the NA85E535 enters the bus hold status. when the NA85E535 has completely entered the bus hold status, the hldakz signal is asserted. while the NA85E535 is in the bus hold status, the hldakz signal stays active. in the bus hold status, the NA85E535 is the bus master of the vsb. the external memory connection pins of the NA85E535 must be designed on the user logic side so that the signals do not conflict in the bus hold status. for the details of the pin statuses in the bus hold status, refer to table 2-8 pin status in each operation mode . when the hldrqz signal is inactive, the NA85E535 enters the normal status. caution make sure that the external bus master accesses sdram during bus hold after the bank precharge command has been executed. (1) bus hold procedure <1> the external memory inputs an external bus hold request signal (hldrqz) to the NA85E535. <2> the NA85E535 outputs the vsb mastership request signal (vaexreq) to the cpu core. <3> the current bus cycle is completed. <4> the cpu core inputs an acknowledge signal (vaack) to the NA85E535 in response to the vaexreq signal. <5> the NA85E535 returns an acknowledge signal (hldakz) to the external memory in response to the hldrqz signal. : bus hold status : <6> the hldrqz signal is deasserted. <7> because the bus hold request from the external memory has been cleared, the hldakz signal is inactive. <8> when the bus cycle in the bus hold status is complete, the vaexreq signal is inactive. <9> the vaack signal from the cpu core is deasserted, and the bus hold status ends. <10> the cpu core is now the master and starts a vsb bus cycle. (2) bus hold timing an example of the bus hold timing is illustrated on the next page. remarks 1. : undetermined status (output), or any level (input) 2. for details of the vsb signals, refer to nu85e hardware user?s manual (a14874e) .
chapter 3 bus control function preliminary user?s manual a15555ej2v0um 92 figure 3-28. bus hold timing vswrite (input) vbclk (input) busclk (output) rdzf (output) vbdo31 to vbdo0 (input) vsbenz3 to vsbenz0 (input) vsseq2 to vsseq0 (input) vsstz (input) a25 to a0 (output) bcystz (output) vdcsz7 to vdcsz0 (input) bus hold status vaexreq (output) vaack (input) hldrqz (input) hldakz (output) di31 to di0 (input) vbdi31 to vbdi0 (output) vsa25 to vsa0 (input) csz7 to csz0 (output) wait wait transfer response rdzr (output) vmlock (output) ready
chapter 3 bus control function preliminary user?s manual a15555ej2v0um 93 3.5 cautions 3.5.1 connection to vsb in a system where two or more bus masters exist on the vsb (vsb multi-master configuration), make sure that the logical sum (or) of each bus master output data (vbdon) and the NA85E535 output data (vbdin) is not input to the input pin (vbdon) of the NA85E535. figure 3-29. example of connection of memc and bus master in vsb multi-master configuration (a) example of recommended connection bus master 1 vbdon vbdin NA85E535 vbdon vbdin bus master 2 vbdon vbdin (b) example of prohibited connection NA85E535 vbdon vbdin bus master 1 vbdon vbdin bus master 2 vbdon vbdin remark n = 31 to 0
chapter 3 bus control function preliminary user?s manual a15555ej2v0um 94 in the following memory access timing, for example, correct data is not input to the NA85E535 in a system with the prohibited connection shown in figure 3-29 (b), because the logical sum (or) of the input data ?d0? from the memory and the input data ?d1? from the vsb is latched at the timing in figure 3-30. figure 3-30. example of memory access timing vbclk (input) vsa25 to vsa0 (input) vswrite (input) vsstz (input) vbdi31 to vbdi0 (output) a25 to a0 (output) csz7 to csz0 (output) rdzf (output) wrz3 to wrz0 (output) bcystz (output) di31 to di0 (input) vsb ? NA85E535 NA85E535 ? memory vdcsz7 to vdcsz0 (input) rdzr (output) do31 to do0 (output) read cycle write cycle a0 vbdo31 to vbdo0 (input) a1 a0 a1 (NA85E535 vsb) d0 (vsb NA85E535) d1 (memory NA85E535) d0 (na85e53 memory) d1 remark : data from memory is latched and output to the vsb. : data from the vsb is latched and output to memory. : sampling timing
chapter 3 bus control function preliminary user?s manual a15555ej2v0um 95 3.5.2 designing high-speed circuit when designing an interface with high-speed clocked external memory (especially sdram) by using the NA85E535, the external read data setup time is very critical. this data setup time can be relaxed in the following ways. ? output the bus clock as quickly as possible (minimize the delay value with respect to the system clock). ? locate the busclk2 and di31 to di0 pins of the NA85E535 and the external pins of the cbic product as closely as possible (as shown in <1> and <2> in figure 3-31), to minimize the delay value. the NA85E535 has a system clock input pin (vbclk2) and a bus clock output pin (busclk2) to support a high- speed memory interface, in addition to the normal system clock input pin (vbclk) and bus clock output pin (busclk). the vbclk2 pin is a clock input pin dedicated to generation of the bus clock output by the busclk2 pin (the logical operations of the busclk2 and busclk signals are the same). the delay time from input of the vbclk2 signal to output of the busclk2 signal is designed to be shorter than the delay time from input of the vbclk signal to output of the busclk signal. to improve the bus clock output delay value of a cbic product, therefore, use the busclk2 signal as the bus clock. figure 3-31. example of measures to relax data setup time (1/2) (a) configuration vbclk vbclk2 NA85E535 delay adjuster delay adjuster vbclk root buffer busclk2 busclk busclk (external pin) di31 to di0 do31 to do0 d31 to d0 (external pins) <1> <2> cbic remarks 1. the specification of the busclk signal of a cbic product can be adjusted by the delay adjuster. 2. shorten the distances between the busclk2 pin of the NA85E535 and external busclk pin (<1>) and between the di31 to di0 pins of the NA85E535 and external d31 to d0 pins (<2>) as much as possible. 3. be sure to input the clock to the vbclk pin.
chapter 3 bus control function preliminary user?s manual a15555ej2v0um 96 figure 3-31. example of measures to relax data setup time (2/2) (b) timing chart vbclk (NA85E535 input) vbclk (root buffer) vbclk (inside NA85E535) busclk (NA85E535 output) vbclk2 (NA85E535 input) busclk2 (NA85E535 output) di31 to di0 (sdram NA85E535) the data read timing can be improved by outputting the busclk2 signal quickly and quickening the data output timing of sdram. latch timing of di31 to di0 signals remark the ac specifications are defined for the delay difference between the vbclk signal output by the root buffer and the vbclk and vbclk2 signals input to the NA85E535 (for details, contact nec).
chapter 3 bus control function preliminary user?s manual a15555ej2v0um 97 3.5.3 processing of data bus the NA85E535 has the dc3r to dc0r and dc3f to dc0f pins to control the data output pins, and the logical sum (or) of these signals can be used to control output of the data i/o pins of the cbic product. however, because these control signals are always high level, except when the external memory is written (the output buffer goes into a high-impedance state), when the internal peripheral i/o is accessed or internal rom is fetched, for example, the data bus goes into a high-impedance state. this means that the dc3r to dc0r and dc3f to dc0f pins can be used to select an output buffer but not to enable an input buffer. to prevent through-current and malfunction of the memory, therefore, externally connect (on the user set board) a buffer with a pull-up function to the i/o buffer for the data bus to pull up the buffer. figure 3-32. processing of data bus NA85E535 din don dn (external pin) cbic dcmr dcmf either of these is necessary remark n = 31 to 0, m = 3 to 0
chapter 3 bus control function preliminary user?s manual a15555ej2v0um 98 3.5.4 dma acknowledge/chip select handling function memory access using the NA85E535 does not execute the vsb cycle and external memory access cycle simultaneously. therefore, the acknowledge/chip select signal output by the dma controller is input to the NA85E535, matched with the actual dma memory cycle, and output in synchronization with the bus clock (busclk). (for details, refer to figures 4-4 to 4-13.) however, the active level of the acknowledge/chip select signal is output only during flyby transfer, and is not output during 2-cycle transfer. for this reason, a selector circuit with the following specifications must be externally connected when 2-cycle transfer and flyby transfer by dma are used together. ? during 2-cycle transfer: outputs the acknowledge/chip select signal output by the dma controller. ? during flyby transfer: outputs the acknowledge/chip select signal output by the NA85E535. this selector circuit must be of a configuration that it has a copy bit of the bit that sets the transfer type of each transfer channel of the dma controller note and selects the corresponding acknowledge/chip select signal. note internal dma controller of cpu core: ttyp bit of dadc0 to dadc3 registers na85e300: ttyp bit of dxadc0 to dxadc3 registers an example of a circuit that selects the acknowledge/chip select signal when the na85e300 is used is shown below. figure 3-33. example of circuit selecting acknowledge/chip select signal (with na85e300) NA85E535 cbic dmxczmmn (during flyby transfer) na85e300 dmxcszn dmxcszmn (during 2-cycle transfer) selector ttyp bit of external dma address control register (dxadcn) (copy register) remark n = 3 to 0, m = 1, 0 in the following cases, handling cannot be performed because the internal system clock is stopped (do not execute dma transfer). ? while the division ratio set by the bus mode control register (bmc) is being switched ? when the pdwn bit of the bmc register is set to 1
preliminary user?s manual a15555ej2v0um 99 chapter 4 memory access timing examples the following pages show examples of memory access timing. table 4-1. examples of memory access timing (1/4) (a) example of sram access timing figure no. read/write cycle access condition page a read cycle ? 104 b write cycle ? 105 c without wait/sequential transfer 106 d without wait/with speculative read 107 e without wait/single transfer/with speculative read/read access to line 108 f without wait/single transfer/with speculative read/read access to another line 109 g without wait/single transfer/with speculative read/write access to line 110 h without wait/single transfer/with speculative read/write access to another line 111 i without wait/single transfer/with speculative read/write access to NA85E535 register 112 j read cycle without wait/eight sequential transfers from speculative read hit address/local bus size: 32 bits 113 k without wait/sequential transfer 114 l data wait = 1/sequential transfer 115 m without wait/non-sequential transfer 116 n data wait = 1/non-sequential transfer 117 4-1 o write cycle without wait/sequential transfer/local bus size: 16 bits 118
chapter 4 memory acc ess timing examples preliminary user?s manual a15555ej2v0um 100 table 4-1. examples of memory access timing (2/4) (b) example of sdram access timing figure no. read/write cycle access condition page a cl = 2/bcw = 2/single transfer 119 b read cycle without wait/cl = 2/sequential transfer/without page and bank change 120 c cl = 2/bcw = 2/single transfer/with page and bank change 121 d without wait/sequential transfer/without page and bank change 122 e without wait/sequential transfer/with bank change 123 f write cycle without wait/non-sequential transfer/without page and bank change 124 g write cycle read cycle cl = 2/bcw = 2/single transfer 125 h read cycle write cycle without wait/cl = 2/single transfer/without page and bank change/with speculative read 126 i without wait/cl = 2/non-sequential transfer/without page and bank change/without speculative read/local bus size: 16 bits 127 j without wait/cl = 2/non-sequential transfer/without page and bank change/with speculative read/local bus size: 8 bits 128 k without wait/cl = 3/sequential transfer/without page and bank change/without speculative read/local bus size: 16 bits 129 l without wait/cl = 3/sequential transfer/without page and bank change/without speculative read/local bus size: 8 bits 130 m read cycle without wait/cl = 2/16 sequential transfers from speculative read hit address/local bus size: 32 bits 131 4-2 n write cycle wit hout wait/sequential transfer/without page and bank change/local bus size: 8 bits 132 (c) example of page rom access timing figure no. access condition page a without speculative read/non-sequential transfer 133 b without speculative read/sequential transfer 134 c with speculative read/non-sequential transfer 135 d with speculative read/sequential transfer 136 e with speculative read/off-page wait = 1/without on-page wait/local bus size: 32 bits (1) 137 4-3 f with speculative read/off-page wait = 1/without on-page wait/local bus size: 32 bits (2) 138
chapter 4 memory acc ess timing examples preliminary user?s manual a15555ej2v0um 101 table 4-1. examples of memory access timing (3/4) (d) example of dma transfer timing (1/2) figure no. transfer type dmac transfer direction transfer condition page a single transfer 139 b single transfer/transfer request during speculative read 140 c single transfer/division by 2 (1) 141 4-4 d sram external i/o single transfer/division by 2 (2) 142 a single transfer 143 4-5 b external i/o sram single transfer/flyby transfer request during write 144 4-6 page rom external i/o single transfer 145 4-7 sdram external i/o single transfer 146 4-8 dmac with on-chip cpu core external i/o sdram single transfer 147 a single transfer 148 4-9 b sram external i/o single transfer (4 words) 149 a single transfer 150 4-10 b external i/o sram single transfer (4 words) 151 4-11 page rom external i/o single transfer (4 words) 152 4-12 sdram external i/o single transfer (4 words) 153 4-13 flyby transfer note 1 na85e300 external i/o sdram single transfer (4 words) 154 a single transfer/without wait/without speculative read 155 b block transfer/with speculative read 156 c block transfer/without speculative read 157 d line transfer/with speculative read 158 4-14 e sram sram line transfer/without speculative read 159 a single transfer/without wait/cl = 2/ without speculative read 160 b block transfer/with speculative read 161 c block transfer/without speculative read 162 d line transfer/with speculative read 163 4-15 e sdram sdram line transfer/without speculative read 164 4-16 sram npb single transfer/with speculative read 165 4-17 npb sram single transfer 166 4-18 2-cycle transfer note 2 dmac with on-chip cpu core npb npb single transfer/during speculative read 167 notes 1. the same cycle is generated in the vsb and local bus regardless of whether speculative read is set. 2. local bus size: 32 bits
chapter 4 memory acc ess timing examples preliminary user?s manual a15555ej2v0um 102 table 4-1. examples of memory access timing (4/4) (d) example of dma transfer timing (2/2) figure no. transfer type dmac transfer direction transfer condition page 4-19 dmac with on- chip cpu core npb ram single transfer/during speculative read 168 a single transfer/without wait/without speculative read 169 b block transfer/with speculative read 170 c block transfer/without speculative read 171 d single transfer (4 words)/with speculative read 172 4-20 e sram sram single transfer (4 words)/without speculative read 173 a single transfer/without wait/cl = 2/without speculative read 174 b block transfer/with speculative read 175 c block transfer/without speculative read 176 d single transfer (4 words)/with speculative read note 2 177 4-21 e 2-cycle transfer note 1 na85e300 sdram sdram single transfer (4 words)/without speculative read note 2 178 notes 1. local bus size: 32 bits 2. the timing is the same regardless of whether speculative read is set. (e) other figure no. title page 4-22 sdram cbr refresh timing 179 4-23 sdram self-refresh timing (stop timing) 180 4-24 mobileram deep power down timing (stop timing) 181 4-25 sdram mode register write operation timing 182 4-26 mobileram expansion mode register write operation timing 183 4-27 bmc register change timing (setting of division by 1 division by 2) 184 4-28 sram write access timing example (if division ratio of busclk for vbclk signal is 1/2) 185
chapter 4 memory acc ess timing examples preliminary user?s manual a15555ej2v0um 103 each timing chart consists of the following states. ? t0 state: vsb start state from cpu core ? t1 and t2 states: basic states ? ta state: address setting wait state ? tw state: wait state ? tact state: state of bank active command ? tbcw state: wait state inserted if bcw = 2 or 3 ? tread state: state of read command ? tlate state: wait state of latency ? tprec state: state of bank precharge command ? twr state: state indicating write command ? wpre state: precharge state after write command ? wend state: state indicating end of write cycle ? tf state: state during dma flyby transfer between sdram and external i/o ? trpw state: state inserted while NA85E535 waits for cycle generation remarks 1. : undetermined status (output), or any level (input) 2. o: sampling timing 3. for details of the vsb signals, refer to nu85e hardware user?s manual (a14874e) . 4. the shaded part in the vsb figure is the same shading of the memory cycle of the corresponding vsb cycle. the transfer response is changed by the vswait, vsahld, and vslast signals as shown in table 4-2. table 4-2. transfer response vswait vsahld vslast transfer response 0 0 0 ready (ready response: current transfer is completed) 1 0 0 wait (wait response) 1 1 0 ahold (address hold response: holds address and control signal) remarks 1. 0: low level, 1: high level 2. the NA85E535 does not have last (last response). 3. if a cache or external bus master is not connected to the cpu core, the vsb data bus size is fixed to 32 bits. as a result, sequential transfer does not take place.
chapter 4 memory acc ess timing examples preliminary user?s manual a15555ej2v0um 104 figure 4-1. example of sram access timing (1/15) (a) read cycle t1 t2 t1 t2 t1 t2 ta tw t1 t2 ti t1 t2 tw vbclk (input) busclk (output) vsa25 to vsa0 (input) vswrite (input) vsbenz3 to vsbenz0 (input) vsctyp2 to vsctyp0 (input) vsstz (input) transfer response vbdi31 to vbdi0 (output) a25 to a0 (output) csz7 to csz0 (output) rdzf (output) wrz3 to wrz0 (output) bcystz (output) benz3 to benz0 (output) dc3r to dc0r (output) di31 to di0 (input) waitz (input) cpu core ? NA85E535 NA85E535 ? sram vdcsz7 to vdcsz0 (input) rdzr (output) dc3f to dc0f (output) (0, 0, 0, 0) (1, 1, 1, 1) (1, 1, 1, 1) (1, 1, 1, 1) (1, 1, 1, 1) (1, 1, 1, 1) (1, 1, 1, 1) (1, 1, 1, 1) (0, 0, 0, 0) (0, 0, 0, 0) (0, 0, 0, 0) (0, 0, 0, 0) d4 t0 t0 t0 t0 t0 d0 d1 d2 d3 wait ready wait ready wait ready wait ahold ready wait ready d0 d1 d2 d3 d4
chapter 4 memory acc ess timing examples preliminary user?s manual a15555ej2v0um 105 figure 4-1. example of sram access timing (2/15) (b) write cycle d0 ready t1 t2 t1 t2 t1 t2 ta tw t1 t2 ti (1, 1, 1, 1) d1 t1 t2 tw d1 (1, 1, 1, 1) (1, 1, 1, 1) wait ready wait ready wait ready wait ready wait d2 d3 d4 wrstbz (output) vbclk (input) busclk (output) transfer response vbdo31 to vbdo0 (input) vsbenz3 to vsbenz0 (input) vsctyp2 to vsctyp0 (input) vswrite (input) vsstz (input) vsa25 to vsa0 (input) vdcsz7 to vdcsz0 (input) cpu core ? NA85E535 a25 to a0 (output) csz7 to csz0 (output) rdzf, rdzr (output) wrz3 to wrz0 (output) bcystz (output) benz3 to benz0 (output) dc3r to dc0r (output) do31 to do0 (output) waitz (input) NA85E535 ? sram h (1, 1, 1, 1) dc3f to dc0f (output) (1, 1, 1, 1) (1, 1, 1, 1) (0, 0, 0, 0) (0, 0, 0, 0) (1, 1, 1, 1) (1, 1, 1, 1) d2 d3 d4 d0 t0
chapter 4 memory acc ess timing examples preliminary user?s manual a15555ej2v0um 106 figure 4-1. example of sram access timing (3/15) (c) read cycle/without wait/sequential transfer ready d0 d1 d2 d3 t1 t2 t1 t2 t1 t2 t1 t2 vsseq2 to vsseq0 (input) (0, 1, 0) a0 (0, 0, 0, 0) ready ready ready wait wait wait vbclk (input) busclk (output) transfer response vbdi31 to vbdi0 (output) vsbenz3 to vsbenz0 (input) vsctyp2 to vsctyp0 (input) vswrite (input) vsstz (input) vsa25 to vsa0 (input) vdcsz7 to vdcsz0 (input) cpu core ? NA85E535 a25 to a0 (output) csz7 to csz0 (output) rdzf (output) wrz3 to wrz0 (output) bcystz (output) benz3 to benz0 (output) dc3r to dc0r (output) di31 to di0 (input) waitz (input) NA85E535 ? sram rdzr (output) (1, 1, 1, 1) dc3f to dc0f (output) (0, 0, 0, 0) a0 + 4h a0 + 8h a0 + ch (0, 0, 1) (0, 0, 1) (0, 0, 0) wait (0, 0, 0, 0) (1, 1, 1, 1) (1, 1, 1, 1) (0, 0, 0, 0) d0 d1 d2 d3 a0 a0 + 4h a0 + 8h a0 + ch t0
chapter 4 memory acc ess timing examples preliminary user?s manual a15555ej2v0um 107 figure 4-1. example of sram access timing (4/15) (d) read cycle/without wait/with speculative read ready d0 d1 d2 d3 t1 t2 t1 t2 t1 t2 t1 t2 (0, 1, 0) a0 (0, 0, 0, 0) ready ready ready wait wait wait ready (0, 0, 0) b0 + 4h (0, 0, 0, 0) d4 d5 d6 d7 (1, 1, 1, 1) vsseq2 to vsseq0 (input) vbclk (input) busclk (output) transfer response vbdi31 to vbdi0 (output) vsbenz3 to vsbenz0 (input) vsctyp2 to vsctyp0 (input) vswrite (input) vsstz (input) vsa25 to vsa0 (input) vdcsz7 to vdcsz0 (input) cpu core ? NA85E535 a25 to a0 (output) csz7 to csz0 (output) rdzf (output) wrz3 to wrz0 (output) bcystz (output) benz3 to benz0 (output) dc3r to dc0r (output) di31 to di0 (input) waitz (input) NA85E535 ? sram rdzr (output) sequential transfer non-sequential transfer (1, 1, 1, 1) (1, 1, 1, 1) dc3f to dc0f (output) (0, 0, 0, 0) (0, 0, 0, 0) a0 + 4h a0 + 8h a0 + ch (0, 0, 1) (0, 0, 1) (0, 0, 0) wait wait a0 a0 + 4h a0 + 8h a0 + ch b0 + 4h b0 + 8h b0 + ch b0 (0, 0, 0, 0) (1, 1, 1, 1) (1, 1, 1, 1) (0, 0, 0, 0) (0, 0, 0, 0) (1, 1, 1, 1) d0 d1 d2 d3 d4 t0 t0 t1 t2 t1 t2 t1 t2 t1 t2
chapter 4 memory acc ess timing examples preliminary user?s manual a15555ej2v0um 108 figure 4-1. example of sram access timing (5/15) (e) read cycle/without wait/single transfer/with speculative read/read access to line ready d0 d1 d2 d3 t1 t2 t1 t2 t1 t2 t1 t2 (0, 0, 0) a0 (0, 0, 0, 0) wait ready wait ready speculative read cycle vsseq2 to vsseq0 (input) vbclk (input) busclk (output) transfer response vbdi31 to vbdi0 (output) vsbenz3 to vsbenz0 (input) vsctyp2 to vsctyp0 (input) vswrite (input) vsstz (input) vsa25 to vsa0 (input) vdcsz7 to vdcsz0 (input) cpu core ? NA85E535 a25 to a0 (output) csz7 to csz0 (output) rdzf (output) wrz3 to wrz0 (output) bcystz (output) benz3 to benz0 (output) dc3r to dc0r (output) di31 to di0 (input) waitz (input) NA85E535 ? sram rdzr (output) (1, 1, 1, 1) dc3f to dc0f (output) (0, 0, 0, 0) a0 + 4h a0 + ch wait (0, 0, 0) (0, 0, 0, 0) read (onto line) read (data bit) a0 a0 + 4h a0 + 8h a0 + ch (0, 0, 0, 0) (1, 1, 1, 1) (1, 1, 1, 1) d0 d3 d1 (0, 0, 0, 0) t0
chapter 4 memory acc ess timing examples preliminary user?s manual a15555ej2v0um 109 figure 4-1. example of sram access timing (6/15) (f) read cycle/without wait/single transfer/with speculative read/read access to another line ready d0 d1 d2 d3 t1 t2 t1 t2 t1 t2 t1 t2 (0, 0, 0) a0 (0, 0, 0, 0) wai t ready wai t ready t1 t2 t1 t2 t1 t2 t1 t2 speculative read cycle speculative read cycle vsseq2 to vsseq0 (input) vbclk (input) busclk (output) transfer response vbdi31 to vbdi0 (output) vsbenz3 to vsbenz0 (input) vsctyp2 to vsctyp0 (input) vswrite (input) vsstz (input) vsa25 to vsa0 (input) vdcsz7 to vdcsz0 (input) cpu core ? NA85E535 a25 to a0 (output) csz7 to csz0 (output) rdzf (output) wrz3 to wrz0 (output) bcystz (output) benz3 to benz0 (output) dc3r to dc0r (output) di31 to di0 (input) waitz (input) NA85E535 ? sram rdzr (output) (1, 1, 1, 1) dc3f to dc0f (output) (0, 0, 0, 0) (0, 0, 0, 0) (0, 0, 0, 0) wai t (0, 0, 0) (0, 0, 0, 0) b0 b0 + 4h (0, 0, 0) (0, 0, 0, 0) read (miss-hit) a0 a0 + 4h a0 + 8h a0 + ch b0 b0 + 4h b0 + 8h b0 + ch (0, 0, 0, 0) (1, 1, 1, 1) (1, 1, 1, 1) d4 d5 d0 d4 d5 d6 d7 t0
chapter 4 memory acc ess timing examples preliminary user?s manual a15555ej2v0um 110 figure 4-1. example of sram access timing (7/15) (g) read cycle/without wait/single transfer/with speculative read/write access to line ready d0 d1 d2 d3 t1 t2 t1 t2 t1 t2 t1 t2 (0, 0, 0) a0 (0, 0, 0, 0) (1, 1, 1, 1) wait ready wait ready t1 t2 t1 t2 d5 d6 wait ready d5 d6 d1 d0 speculative read cycle speculative read cycle (re-execution) vsseq2 to vsseq0 (input) vbclk (input) busclk (output) transfer response vbdi31 to vbdi0 (output) vsbenz3 to vsbenz0 (input) vsctyp2 to vsctyp0 (input) vswrite (input) vsstz (input) vsa25 to vsa0 (input) vdcsz7 to vdcsz0 (input) cpu core ? NA85E535 a25 to a0 (output) csz7 to csz0 (output) rdzf (output) wrz3 to wrz0 (output) bcystz (output) benz3 to benz0 (output) dc3r to dc0r (output) do31 to do0 (output) waitz (input) NA85E535 ? sram rdzr (output) di31 to di0 (input) wrstbz (output) (0, 0, 0, 0) dc3f to dc0f (output) (1, 1, 1, 1) wait a0 + 8h a0 + ch (0, 0, 0) (0, 0, 0, 0) a0 + 4h (0, 0, 0) (0, 0, 0, 0) write buffering (onto speculative read line) read (onto speculative read line) a0 a0 + 4h a0 + 8h a0 + ch a0 + 8h a0 + ch a0 + 4h a0 + 8h a0 + ch a0 (1, 1, 1, 1) d5 (0, 0, 0, 0) (1, 1, 1, 1) d6 (1, 1, 1, 1) d1 d0 vbdo31 to vbdo0 (input) t0 t1 t2 t1 t2 t1 t2 t1 t2
chapter 4 memory acc ess timing examples preliminary user?s manual a15555ej2v0um 111 figure 4-1. example of sram access timing (8/15) (h) read cycle/without wait/single transfer/with speculative read/write access to another line speculative read cycle ready d0 d1 d2 d3 t1 t2 t1 t2 t1 t2 t1 t2 (0, 0, 0) a0 (0, 0, 0, 0) (1, 1, 1, 1) wait ready wait ready t1 t2 t1 t2 d0 d1 wait ready vsseq2 to vsseq0 (input) vbclk (input) busclk (output) transfer response vbdi31 to vbdi0 (output) vsbenz3 to vsbenz0 (input) vsctyp2 to vsctyp0 (input) vswrite (input) vsstz (input) vsa25 to vsa0 (input) vdcsz7 to vdcsz0 (input) cpu core ? NA85E535 a25 to a0 (output) csz7 to csz0 (output) rdzf (output) wrz3 to wrz0 (output) bcystz (output) benz3 to benz0 (output) dc3r to dc0r (output) do31 to do0 (output) waitz (input) NA85E535 ? sram rdzr (output) di31 to di0 (input) wrstbz (output) (1, 1, 1, 1) (0, 0, 0, 0) dc3f to dc0f (output) (0, 0, 0, 0) wait b0 b1 (0, 0, 0) (0, 0, 0, 0) a0 + 4h (0, 0, 0) (0, 0, 0, 0) data hit write buffering a0 a0 + 4h a0 + 8h a0 + ch b0 b1 (0, 0, 0, 0) (1, 1, 1, 1) (1, 1, 1, 1) (1, 1, 1, 1) d0 (0, 0, 0, 0) d1 d1 d0 vbdo31 to vbdo0 (input) t0 (1, 1, 1, 1)
chapter 4 memory acc ess timing examples preliminary user?s manual a15555ej2v0um 112 figure 4-1. example of sram access timing (9/15) (i) read cycle/without wait/single transfer/with speculative read/write access to NA85E535 register ready d0 d1 d2 d3 t1 t2 t1 t2 t1 t2 t1 t2 a0 wait speculative read cycle vbclk (input) busclk (output) transfer response vbdi31 to vbdi0 (output) vpretr (output) vpstb (input) vswrite (input) vsstz (input) vsa25 to vsa0 (input) vdcsz7 to vdcsz0 (input) cpu core ? NA85E535 a25 to a0 (output) csz7 to csz0 (output) rdzf (output) wrz3 to wrz0 (output) bcystz (output) benz3 to benz0 (output) dc3r to dc0r (output) waitz (input) NA85E535 ? sram rdzr (output) di31 to di0 (input) (1, 1, 1, 1) dc3f to dc0f (output) (0, 0, 0, 0) wait (3fff480h) retry to npb ready a0 a0 + 4h a0 + 8h a0 + ch (0, 0, 0, 0) (1, 1, 1, 1) (1, 1, 1, 1) (0, 0, 0, 0) d0 t0
chapter 4 memory acc ess timing examples preliminary user?s manual a15555ej2v0um 113 figure 4-1. example of sram access timing (10/15) (j) read cycle/without wait/8 times of sequential transfer from speculative read hit address/local bus size: 32 bits d0 d1 d2 d3 t1 t2 t1 t2 t1 t2 t1 t2 (0, 0, 0) a0 (0, 0, 0, 0) speculative read cycle vsseq2 to vsseq0 (input) vbclk (input) busclk (output) transfer response vbdi31 to vbdi0 (output) vsbenz3 to vsbenz0 (input) vsctyp2 to vsctyp0 (input) vswrite (input) vsstz (input) vsa25 to vsa0 (input) vdcsz7 to vdcsz0 (input) cpu core ? NA85E535 a25 to a0 (output) csz7 to csz0 (output) rdzf (output) wrz3 to wrz0 (output) bcystz (output) benz3 to benz0 (output) dc3r to dc0r (output) waitz (input) NA85E535 ? sram rdzr (output) di31 to di0 (input) dc3f to dc0f (output) t0 (0, 0, 1) d0 d0 d1 d2 d4 d5 d6 d7 t1 t2 t2 t1 t2 t1 t2 t1 t2 (0, 0, 0, 0) (1, 1, 1, 1) (0, 0, 0, 0) (1, 1, 1, 1) d4 d5 d6 d7 speculative read cycle a0 a0 + 4h a0 + 8h a0 + ch (1, 1, 1, 1) (0, 0, 0, 0) (1, 1, 1, 1) (1, 1, 1, 1) (1, 1, 1, 1) (0, 0, 0, 0) a0 + 10h a0 + 10h a0 + 14h a0 + 18h a0 + 1ch (1, 1, 1, 1) (0, 0, 0, 0) (1, 1, 1, 1) a0 a0 + 4h a0 + 8h a0 + ch a0 + 10h a0 + 14h a0 + 18h a0 + 1ch (0, 0, 0) (0, 1, 1) speculative read hit ready wai t ready wai t ready wai t ready wai t ready ready wai t wai t d3 wai t (0, 0, 0, 0) (0, 0, 0, 0) (0, 0, 0, 0)
chapter 4 memory acc ess timing examples preliminary user?s manual a15555ej2v0um 114 figure 4-1. example of sram access timing (11/15) (k) write cycle/without wait/sequential transfer d0 (1, 1, 1, 1) wait t1 t2 t1 t2 t1 t2 t1 t2 (0, 0, 1) (0, 0, 1) (0, 0, 0) a0 + 4h a0 + 8h a0 + ch (0, 0, 0, 0) d0 wait (0, 0, 1) (0, 0, 1) (0, 0, 0) a0 + 4h a0 + 8h a0 + ch (0, 0, 0, 0) d4 (0, 0, 1) (0, 0, 1) (0, 0, 0) b0 + 4h b0 + 8h b0 + ch (0, 0, 0, 0) wait (1, 1, 1, 1) t1 t2 t1 t2 t1 t2 t1 t2 t1 t2 t1 t2 t1 t2 t1 t2 wrstbz (output) vbclk (input) busclk (output) transfer response vbdo31 to vbdo0 (input) vsbenz3 to vsbenz0 (input) vsctyp2 to vsctyp0 (input) vswrite (input) vsstz (input) vsa25 to vsa0 (input) vdcsz7 to vdcsz0 (input) cpu core ? NA85E535 a25 to a0 (output) csz7 to csz0 (output) rdzf, rdzr (output) wrz3 to wrz0 (output) bcystz (output) benz3 to benz0 (output) dc3r to dc0r (output) do31 to do0 (output) waitz (input) NA85E535 ? sram vsseq2 to vsseq0 (input) h (1, 1, 1, 1) (1, 1, 1, 1) (1, 1, 1, 1) dc3f to dc0f (output) (1, 1, 1, 1) a0 (0, 1, 0) ready d1 d2 d3 a0 a0 + 4h a0 + 8h a0 + ch (1, 1, 1, 1) (1, 1, 1, 1) (0, 0, 0, 0) (0, 0, 0, 0) (0, 0, 0, 0) d0 d1 d2 d3 (1, 1, 1, 1) a0 b0 (0, 1, 0) (0, 1, 0) ready ready d1 d2 d3 d5 d6 d7 a0 a0 + 4h a0 + 8h a0 + ch b0 b0 + 4h b0 + 8h b0 + ch (1, 1, 1, 1) (1, 1, 1, 1) (1, 1, 1, 1) (1, 1, 1, 1) (1, 1, 1, 1) (1, 1, 1, 1) (1, 1, 1, 1) (1, 1, 1, 1) (1, 1, 1, 1) (0, 0, 0, 0) (0, 0, 0, 0) (0, 0, 0, 0) d0 d1 d2 d3 d4 d5 d6 d7 t0 t0
chapter 4 memory acc ess timing examples preliminary user?s manual a15555ej2v0um 115 figure 4-1. example of sram access timing (12/15) (l) write cycle/data wait = 1/sequential transfer d0 d0 (1, 1, 1, 1) wai t d1 d2 d3 t1 t2 t1 t2 t1 t2 t1 t2 (0, 0, 1) (0, 0, 1) (0, 0, 0) a0 + 4h a0 + 8h a0 + ch a0 a0 + 4h a0 + 8h a0 + ch (0, 0, 0, 0) tw tw tw tw b0 + 4h b0 + ch wai t wai t (0, 0, 1) (0, 0, 0) d4 d5 d6 d7 b0 b0 + 4h b0 + 8h b0 + ch t1 t2 t1 t2 t1 t2 t1 t2 tw tw tw tw d4 d6 wrstbz (output) vbclk (input) busclk (output) transfer response vbdo31 to vbdo0 (input) vsbenz3 to vsbenz0 (input) vsctyp2 to vsctyp0 (input) vswrite (input) vsstz (input) vsa25 to vsa0 (input) vdcsz7 to vdcsz0 (input) cpu core ? NA85E535 a25 to a0 (output) csz7 to csz0 (output) rdzf, rdzr (output) wrz3 to wrz0 (output) bcystz (output) benz3 to benz0 (output) dc3r to dc0r (output) do31 to do0 (output) waitz (input) NA85E535 ? sram vsseq2 to vsseq0 (input) h (1, 1, 1, 1) dc3f to dc0f (output) (1, 1, 1, 1) a0 b0 b0 + 8h (0, 1, 0) (0, 1, 0) (0, 0, 1) ready ready d1 d2 d3 d5 d7 (1, 1, 1, 1) (1, 1, 1, 1) (0, 0, 0, 0) (1, 1, 1, 1) (1, 1, 1, 1) (0, 0, 0, 0) (0, 0, 0, 0) (1, 1, 1, 1) (1, 1, 1, 1) (0, 0, 0, 0) (1, 1, 1, 1) (1, 1, 1, 1) t0 ready wai t ready
chapter 4 memory acc ess timing examples preliminary user?s manual a15555ej2v0um 116 figure 4-1. example of sram access timing (13/15) (m) write cycle/without wait/non-sequential transfer d0 ready (1, 1, 1, 1) wai t d1 d2 d3 t1 t2 t1 t2 t1 t2 t1 t2 ready wai t ready wai t ready wai t wrstbz (output) vbclk (input) busclk (output) transfer response vbdo31 to vbdo0 (input) vsbenz3 to vsbenz0 (input) vsctyp2 to vsctyp0 (input) vswrite (input) vsstz (input) vsa25 to vsa0 (input) vdcsz7 to vdcsz0 (input) cpu core ? NA85E535 a25 to a0 (output) csz7 to csz0 (output) rdzf, rdzr (output) wrz3 to wrz0 (output) bcystz (output) benz3 to benz0 (output) dc3r to dc0r (output) do31 to do0 (output) waitz (input) NA85E535 ? sram vsseq2 to vsseq0 (input) h (1, 1, 1, 1) dc3f to dc0f (output) (1, 1, 1, 1) a0 a0 + 4h a0 + 8h a0 + ch (0, 0, 0) (0, 0, 0, 0) a0 a0 + 4h a0 + 8h a0 + ch (1, 1, 1, 1) (1, 1, 1, 1) (1, 1, 1, 1) (1, 1, 1, 1) (0, 0, 0, 0) (0, 0, 0, 0) (0, 0, 0, 0) d0 d1 d2 d3 t0
chapter 4 memory acc ess timing examples preliminary user?s manual a15555ej2v0um 117 figure 4-1. example of sram access timing (14/15) (n) write cycle/data wait = 1/non-sequential transfer d0 (1, 1, 1, 1) d1 d3 d2 a0 a0 + 4h a0 + 8h a0 + ch d0 ready wait d1 d2 d3 ready wait ready wait ready wait t1 t2 tw t1 t2 tw t1 t2 tw t1 t2 tw wrstbz (output) vbclk (input) busclk (output) transfer response vbdo31 to vbdo0 (input) vsbenz3 to vsbenz0 (input) vsctyp2 to vsctyp0 (input) vswrite (input) vsstz (input) vsa25 to vsa0 (input) vdcsz7 to vdcsz0 (input) cpu core ? NA85E535 a25 to a0 (output) csz7 to csz0 (output) rdzf, rdzr (output) wrz3 to wrz0 (output) bcystz (output) benz3 to benz0 (output) dc3r to dc0r (output) do31 to do0 (output) waitz (input) NA85E535 ? sram vsseq2 to vsseq0 (input) (1, 1, 1, 1) dc3f to dc0f (output) h a0 a0 + 4h a0 + 8h a0 + ch (0, 0, 0) (0, 0, 0, 0) (1, 1, 1, 1) (1, 1, 1, 1) (0, 0, 0, 0) (0, 0, 0, 0) (0, 0, 0, 0) (1, 1, 1, 1) (1, 1, 1, 1) t0 (1, 1, 1, 1)
chapter 4 memory acc ess timing examples preliminary user?s manual a15555ej2v0um 118 figure 4-1. example of sram access timing (15/15) (o) write cycle/without wait/sequential transfer/local bus size: 16 bits d0 (1, 1, 1, 1) wait t1 t2 (0, 0, 1) (0, 0, 1) (0, 0, 0) a0 + 4h a0 + 8h a0 + ch (0, 0, 0, 0) wrstbz (output) vbclk (input) busclk (output) transfer response vbdo31 to vbdo0 (input) vsbenz3 to vsbenz0 (input) vsctyp2 to vsctyp0 (input) vswrite (input) vsstz (input) vsa25 to vsa0 (input) vdcsz7 to vdcsz0 (input) cpu core ? NA85E535 a25 to a0 (output) csz7 to csz0 (output) rdzf, rdzr (output) wrz3 to wrz0 (output) bcystz (output) benz3 to benz0 (output) dc3r to dc0r (output) do31 to do0 (output) waitz (input) NA85E535 ? sram vsseq2 to vsseq0 (input) t1 t2 t1 t2 t1 t2 h (1, 1, 1, 1) dc3f to dc0f (output) (1, 1, 1, 1) a0 (0, 1, 0) ready d1 d2 d3 a0 a0 + 2h (1, 1, 1, 1) (1, 1, 0, 0) (1, 1, 0, 0) d0 (a0) d0 (a0 + 2h) a0 + 4h a0 + 8h a0 + ch a0 + 6h a0 + ah a0 + eh (1, 1, 1, 1) (1, 1, 0, 0) (1, 1, 0, 0) (1, 1, 1, 1) (1, 1, 1, 1) (1, 1, 0, 0) (1, 1, 0, 0) (1, 1, 0, 0) (1, 1, 0, 0) d1 (a0 + 4h) d1 (a0 + 6h) d2 (a0 + 8h) d2 (a0 + ah) d3 (a0 + ch) d3 (a0 + eh) t0 t1 t2 t1 t2 t1 t2 t1 t2 (1, 1, 1, 1) (1, 1, 1, 1) (1, 1, 0, 0) (1, 1, 0, 0) (0, 0, 0, 0) (1, 1, 1, 1) (1, 1, 1, 1)
chapter 4 memory acc ess timing examples preliminary user?s manual a15555ej2v0um 119 figure 4-2. example of sdram access timing (1/14) (a) read cycle/cl = 2/bcw = 2/single transfer ready d0 wait d1 tread (0, 0, 0, 0) bank a d2 (0, 0, 0, 0) tlate tlate tact tbcw tact tbcw tbcw tread tlate tlate tprec tact tbcw tread tlate tlate ready wait wait bcw bcw bcw bcw bank active command (bank a) read command bank active command (bank a) read command bank precharge command (bank a) bank active command (bank b) read command bank precharge command (bank a) bank a bank a bank b bank a latency = 2 latency = 2 latency = 2 vsseq2 to vsseq0 (input) vbclk (input) busclk (output) transfer response vbdi31 to vbdi0 (output) vsbenz3 to vsbenz0 (input) vsctyp2 to vsctyp0 (input) vswrite (input) vsstz (input) vsa25 to vsa0 (input) vdcsz7 to vdcsz0 (input) cpu core ? NA85E535 a25 to a0 (output) csz7 to csz0 (output) sdrasz (output) dqm3 to dqm0 (output) bcystz (output) benz3 to benz0 (output) dc3f to dc0f (output) NA85E535 ? sdram sdwez (output) di31 to di0 (input) sdcasz (output) (1, 1, 1, 1) (0, 0, 0, 0) (1, 1, 1, 1) (0, 0, 0, 0) (1, 1, 1, 1) dc3r to dc0r (output) (0, 0, 0, 0) (0, 0, 0) (0, 0, 0) (0, 0, 0, 0) (0, 0, 0) ready bank change page change col (1, 1, 1, 1) (0, 0, 0, 0) (1, 1, 1, 1) (1, 1, 1, 1) col (1, 1, 1, 1) (0, 0, 0, 0) col (0, 0, 0, 0) d0 d1 d2 t0 t0 t0
chapter 4 memory acc ess timing examples preliminary user?s manual a15555ej2v0um 120 figure 4-2. example of sdram access timing (2/14) (b) read cycle/without wait/cl = 2/sequential transfer/without page and bank change d0 wait d1 tread (0, 0, 1) (0, 0, 1) (0, 0, 0) a0 + 4h a0 + 8h a0 + ch col (a0 + 4h) (0, 0, 0, 0) (1, 1, 1, 1) col (a0) col (a0 + 8h) col (a0 + ch) h d2 d3 tread tread tread tlate tlate h latency = 2 vsseq2 to vsseq0 (input) vbclk (input) busclk (output) transfer response vbdi31 to vbdi0 (output) vsbenz3 to vsbenz0 (input) vsctyp2 to vsctyp0 (input) vswrite (input) vsstz (input) vsa25 to vsa0 (input) vdcsz7 to vdcsz0 (input) cpu core ? NA85E535 a25 to a0 (output) csz7 to csz0 (output) sdrasz (output) dqm3 to dqm0 (output) bcystz (output) benz3 to benz0 (output) dc3f to dc0f (output) NA85E535 ? sdram sdwez (output) di31 to di0 (input) sdcasz (output) dc3r to dc0r (output) (0, 0, 0, 0) a0 (0, 1, 0) ready (0, 0, 0, 0) (0, 0, 0, 0) (1, 1, 1, 1) d0 d1 d2 d3 t0 (0, 0, 0, 0)
chapter 4 memory acc ess timing examples preliminary user?s manual a15555ej2v0um 121 figure 4-2. example of sdram access timing (3/14) (c) write cycle/cl = 2/bcw = 2/single transfer/with page and bank change d0 ready wait twr (0, 0, 0, 0) bank a (0, 0, 0, 0) tact tbcw tw tact tbcw tbcw twr tprec tw tact tbcw wpre wend ready wait bcw bcw bcw bcw bank active command (bank a) write command bank active command (bank a) write command bank precharge command (bank a) bank active command (bank b) write command bank precharge command (bank a) bank a bank a twr ready wait d1 d2 bank b bank a (0, 0, 0, 0) (0, 0, 0, 0) vsseq2 to vsseq0 (input) vbclk (input) busclk (output) transfer response vbdo31 to vbdo0 (input) vsbenz3 to vsbenz0 (input) vsctyp2 to vsctyp0 (input) vswrite (input) vsstz (input) vsa25 to vsa0 (input) vdcsz7 to vdcsz0 (input) cpu core ? NA85E535 a25 to a0 (output) csz7 to csz0 (output) sdrasz (output) dqm3 to dqm0 (output) bcystz (output) benz3 to benz0 (output) dc3f to dc0f (output) NA85E535 ? sdram sdwez (output) do31 to do0 (output) sdcasz (output) (1, 1, 1, 1) (1, 1, 1, 1) (1, 1, 1, 1) (0, 0, 0, 0) dc3r to dc0r (output) (0, 0, 0) (0, 0, 0, 0) page change bank change col (1, 1, 1, 1) col (0, 0, 0, 0) col (1, 1, 1, 1) t0 d0 d1 d2 (1, 1, 1, 1)
chapter 4 memory acc ess timing examples preliminary user?s manual a15555ej2v0um 122 figure 4-2. example of sdram access timing (4/14) (d) write cycle/without wait/sequential transfer/without page and bank change d7 d0 wait d1 tw twr (0, 0, 1) (0, 0, 1) (0, 0, 0) a0 + 4h a0 + 8h a0 + ch (0, 0, 0, 0) (0, 0, 0, 0) (0, 0, 0, 0) d0 wait (0, 0, 1) (0, 0, 1) (0, 0, 0) a0 + 4h a0 + 8h a0 + ch (0, 0, 0, 0) d4 (0, 0, 1) (0, 0, 1) (0, 0, 0) b0 + 4h b0 + 8h b0 + ch (0, 0, 0, 0) wait twr twr twr d2 d3 d1 tw twr (0, 0, 0, 0) (0, 0, 0, 0) twr twr twr d2 d3 tw twr twr twr twr d4 d5 d6 write command write command write command write command write command write command write command write command write command write command write command write command tw vsseq2 to vsseq0 (input) vbclk (input) busclk (output) transfer response vbdo31 to vbdo0 (input) vsbenz3 to vsbenz0 (input) vsctyp2 to vsctyp0 (input) vswrite (input) vsstz (input) vsa25 to vsa0 (input) vdcsz7 to vdcsz0 (input) cpu core ? NA85E535 a25 to a0 (output) csz7 to csz0 (output) sdrasz (output) dqm3 to dqm0 (output) bcystz (output) benz3 to benz0 (output) dc3r to dc0r (output) NA85E535 ? sdram sdwez (output) do31 to do0 (output) sdcasz (output) h (1, 1, 1, 1) (1, 1, 1, 1) (0, 0, 0, 0) dc3f to dc0f (output) (1, 1, 1, 1) a0 (0, 1, 0) ready d1 d2 d3 d0 (0, 0, 0, 0) a0 b0 (0, 1, 0) (0, 1, 0) ready ready d1 d2 d3 d5 d6 d7 d0 (0, 0, 0, 0) (1, 1, 1, 1) (0, 0, 0, 0) (0, 0, 0, 0) t0 t0 a0 col (a0) col (a0 + 8h) col (a0 + ch) col (a0 + 4h) (1, 1, 1, 1) a0 col (a0 + 4h) col (a0) col (a0 + 8h) col (a0 + ch) col (b0 + 4h) col (b0) col (b0 + 8h) col (b0 + ch)
chapter 4 memory acc ess timing examples preliminary user?s manual a15555ej2v0um 123 figure 4-2. example of sdram access timing (5/14) (e) write cycle/without wait/sequential transfer/with bank change d0 wait d1 twr (0, 0, 1) (0, 0, 1) (0, 0, 0) a0 + 4h a0 + 8h a0 + ch (0, 0, 0, 0) (0, 0, 0, 0) twr twr twr d2 (0, 0, 0, 0) tact wpre wend twr twr twr twr d6 d7 d5 b0 + 4h b0 + 8h b0 + ch wait write command write command write command write command write command write command write command write command tw tw vsseq2 to vsseq0 (input) vbclk (input) busclk (output) transfer response vbdo31 to vbdo0 (input) vsbenz3 to vsbenz0 (input) vsctyp2 to vsctyp0 (input) vswrite (input) vsstz (input) vsa25 to vsa0 (input) vdcsz7 to vdcsz0 (input) cpu core ? NA85E535 a25 to a0 (output) csz7 to csz0 (output) sdrasz (output) dqm3 to dqm0 (output) bcystz (output) benz3 to benz0 (output) dc3r to dc0r (output) NA85E535 ? sdram sdwez (output) do31 to do0 (output) sdcasz (output) (1, 1, 1, 1) dc3f to dc0f (output) a0 b0 ready ready d1 d3 d4 d5 d6 d7 (0, 1, 0) (0, 0, 0, 0) bank change d0 d3 d4 (0, 0, 0, 0) bank precharge command (bank a) t0 d2 col (a0 + 4h) col (a0) col (a0 + 8h) col (a0 + ch) bank a bank b col (b0 + 4h) col (b0) col (b0 + 8h) col (b0 + ch) (1, 1, 1, 1)
chapter 4 memory acc ess timing examples preliminary user?s manual a15555ej2v0um 124 figure 4-2. example of sdram access timing (6/14) (f) write cycle/without wait/non-sequential transfer/without page and bank change d0 ready d0 wait d1 d1 twr twr twr twr h d2 d3 ready wait ready wait ready wait d2 d3 write command write command write command write command (0, 0, 0, 0) (1, 1, 1, 1) (0, 0, 0, 0) (1, 1, 1, 1) (0, 0, 0, 0) (1, 1, 1, 1) (0, 0, 0, 0) (0, 0, 0, 0) (1, 1, 1, 1) (0, 0, 0, 0) (1, 1, 1, 1) (0, 0, 0, 0) (1, 1, 1, 1) (0, 0, 0, 0) (0, 0, 0, 0) (1, 1, 1, 1) (0, 0, 0, 0) (1, 1, 1, 1) (0, 0, 0, 0) (1, 1, 1, 1) (0, 0, 0, 0) vsseq2 to vsseq0 (input) vbclk (input) busclk (output) transfer response vbdo31 to vbdo0 (input) vsbenz3 to vsbenz0 (input) vsctyp2 to vsctyp0 (input) vswrite (input) vsstz (input) vsa25 to vsa0 (input) vdcsz7 to vdcsz0 (input) cpu core ? NA85E535 a25 to a0 (output) csz7 to csz0 (output) sdrasz (output) dqm3 to dqm0 (output) bcystz (output) benz3 to benz0 (output) dc3r to dc0r (output) NA85E535 ? sdram sdwez (output) do31 to do0 (output) sdcasz (output) dc3f to dc0f (output) (1, 1, 1, 1) a0 a0 + 4h a0 + 8h a0 + ch (0, 0, 0) (0, 0, 0, 0) (0, 0, 0, 0) t0 t0 t0 t0 col (a0 + 4h) col (a0) col (a0 + 8h) col (a0 + ch) (1, 1, 1, 1) (1, 1, 1, 1) (1, 1, 1, 1)
chapter 4 memory acc ess timing examples preliminary user?s manual a15555ej2v0um 125 figure 4-2. example of sdram access timing (7/14) (g) write cycle read cycle/cl = 2/bcw = 2/single transfer d0 ready wait twr (0, 0, 0, 0) bank a (0, 0, 0, 0) tact tbcw tw tact tbcw tbcw twr tprec tw tact tbcw tlate tlate ready wait bank active command (bank a) write command bank active command (bank a) write command bank precharge command (bank a) bank active command (bank b) read command bank precharge command (bank a) bank a bank a tread ready wait d1 bank b bank a (0, 0, 0, 0) (1, 1, 1, 1) (0, 0, 0, 0) (0, 0, 0, 0) (1, 1, 1, 1) d0 vsseq2 to vsseq0 (input) vbclk (input) busclk (output) transfer response vbdo31 to vbdo0 (input) vsbenz3 to vsbenz0 (input) vsctyp2 to vsctyp0 (input) vswrite (input) vsstz (input) vsa25 to vsa0 (input) vdcsz7 to vdcsz0 (input) cpu core ? NA85E535 a25 to a0 (output) csz7 to csz0 (output) sdrasz (output) dqm3 to dqm0 (output) bcystz (output) benz3 to benz0 (output) dc3r to dc0r (output) NA85E535 ? sdram sdwez (output) do31 to do0 (output) sdcasz (output) vbdi31 to vbdi0 (output) di31 to di0 (input) bcw bcw bcw bcw (1, 1, 1, 1) (1, 1, 1, 1) dc3f to dc0f (output) (0, 0, 0) (0, 0, 0, 0) page change col col col (1, 1, 1, 1) (0, 0, 0, 0) (1, 1, 1, 1) d0 t0 bank change latency = 2 d0 d1
chapter 4 memory acc ess timing examples preliminary user?s manual a15555ej2v0um 126 figure 4-2. example of sdram access timing (8/14) (h) read cycle write cycle/without wait/cl = 2/single transfer/without page and bank change/with speculative read ready d0 wait d1 tread col (a0 + 4h) (1, 1, 1, 1) col (a0 + 8h) col (a0 + ch) h d2 d3 tread tread tread tlate tlate tw twr d4 ready wait vsseq2 to vsseq0 (input) vbclk (input) busclk (output) transfer response vbdo31 to vbdo0 (input) vsbenz3 to vsbenz0 (input) vsctyp2 to vsctyp0 (input) vswrite (input) vsstz (input) vsa25 to vsa0 (input) vdcsz7 to vdcsz0 (input) cpu core ? NA85E535 a25 to a0 (output) csz7 to csz0 (output) sdrasz (output) dqm3 to dqm0 (output) bcystz (output) benz3 to benz0 (output) dc3r to dc0r (output) NA85E535 ? sdram sdwez (output) sdcasz (output) vbdi31 to vbdi0 (output) di31 to di0 (input) latency = 2 (1, 1, 1, 1) dc3f to dc0f (output) (0, 0, 0, 0) (0, 0, 0, 0) a0 b0 (0, 0, 0) (0, 0, 0, 0) (0, 0, 0) (0, 0, 0, 0) (0, 0, 0, 0) (0, 0, 0, 0) d0 read cycle write cycle do31 to do0 (output) d4 t0 col (a0) (1, 1, 1, 1)
chapter 4 memory acc ess timing examples preliminary user?s manual a15555ej2v0um 127 figure 4-2. example of sdram access timing (9/14) (i) read cycle/without wait/cl = 2/non-sequential transfer/without page and bank change/without speculative read/local bus size : 16 bits d0 ready d0 (a0) d0 (a0 + 2h) tread (0, 0, 0) a0 (0, 0, 0, 0) col (a0) h tread tlate tlate col (a0 + 2h) vsseq2 to vsseq0 (input) vbclk (input) busclk (output) transfer response vbdi31 to vbdi0 (output) vsbenz3 to vsbenz0 (input) vsctyp2 to vsctyp0 (input) vswrite (input) vsstz (input) vsa25 to vsa0 (input) vdcsz7 to vdcsz0 (input) cpu core ? NA85E535 a25 to a0 (output) csz7 to csz0 (output) sdrasz (output) dqm3 to dqm0 (output) bcystz (output) benz3 to benz0 (output) dc3r to dc0r (output) NA85E535 ? sdram sdwez (output) sdcasz (output) di31 to di0 (input) h latency = 2 (1, 1, 1, 1) dc3f to dc0f (output) (0, 0, 0, 0) wait (1, 1, 0, 0) (1, 1, 1, 1) (0, 0, 0, 0) t0 (0, 0, 0, 0)
chapter 4 memory acc ess timing examples preliminary user?s manual a15555ej2v0um 128 figure 4-2. example of sdram access timing (10/14) (j) read cycle/without wait/cl = 2/non-sequential transfer/without page and bank change/with speculative read/local bus size: 8 bits d0 ready d0 (a0) tread (0, 0, 0) a0 col (a0 + 4h) (0, 0, 0, 0) (1, 1, 1, 0) (1, 1, 1, 1) col (a0 + 8h) col (a0 + ch) tread tread tread tlate tlate col (a0 + 5h) col (a0 + 6h) col (a0 + 7h) col (a0 + 9h) col (a0 + ah) col (a0 + bh) col (a0 + fh) col (a0 + dh) col (a0 + eh) tread tread tread tread tread tread tread tread tread tread tread tread vsseq2 to vsseq0 (input) vbclk (input) busclk (output) transfer response vbdi31 to vbdi0 (output) vsbenz3 to vsbenz0 (input) vsctyp2 to vsctyp0 (input) vswrite (input) vsstz (input) vsa25 to vsa0 (input) vdcsz7 to vdcsz0 (input) cpu core ? NA85E535 a25 to a0 (output) csz7 to csz0 (output) sdrasz (output) dqm3 to dqm0 (output) bcystz (output) benz3 to benz0 (output) dc3f to dc0f (output) NA85E535 ? sdram sdwez (output) sdcasz (output) di31 to di0 (input) d0 (a0 + 1h) d0 (a0 + 2h) d0 (a0 + 3h) d1 (a0 + 4h) d1 (a0 + 5h) d1 (a0 + 6h) d1 (a0 + 7h) d2 (a0 + 8h) d2 (a0 + 9h) d2 (a0 + ah) d2 (a0 + bh) d3 ( a0 + ch) d3 ( a0 + dh) d3 ( a0 + eh) d3 ( a0 + fh) h latency = 2 h (1, 1, 1, 1) dc3r to dc0r (output) (0, 0, 0, 0) wait (0, 0, 0, 0) (1, 1, 1, 1) (0, 0, 0, 0) t0 col (a0) col (a0 + 1h) col (a0 + 2h) col (a0 + 3h)
chapter 4 memory acc ess timing examples preliminary user?s manual a15555ej2v0um 129 figure 4-2. example of sdram access timing (11/14) (k) read cycle/without wait/cl = 3/sequential transfer/without page and bank change/without speculative read/local bus size: 16 bits d0 ready wait tread (1, 1, 0, 0) (1, 1, 1, 1) (0, 0, 0, 0) ready wait tlate ready wait ready wait vsseq2 to vsseq0 (input) vbclk (input) busclk (output) transfer response vbdi31 to vbdi0 (output) vsbenz3 to vsbenz0 (input) vsctyp2 to vsctyp0 (input) vswrite (input) vsstz (input) vsa25 to vsa0 (input) vdcsz7 to vdcsz0 (input) cpu core ? NA85E535 a25 to a0 (output) csz7 to csz0 (output) sdrasz (output) dqm3 to dqm0 (output) bcystz (output) benz3 to benz0 (output) dc3r to dc0r (output) NA85E535 ? sdram sdwez (output) sdcasz (output) d1 d2 d3 tread tread tread tread tread tread tread tlate tlate h h d0 (a0) latency = 3 dc3f to dc0f (output) di31 to di0 (input) d0 (a0 + 2h) d1 (a0 + 4h) d1 (a0 + 6h) d2 (a0 + 8h) d2 (a0 + ah) d3 (a0 + ch) d3 (a0 + eh) (0, 0, 0, 0) a0 a0 + 4h a0 + 8h a0 + ch (0, 1, 0) (0, 0, 0, 0) (0, 0, 1) (0, 0, 0) (0, 0, 0, 0) (0, 0, 0, 0) (0, 0, 1) (0, 0, 0, 0) (0, 0, 0, 0) t0 (1, 1, 1, 1) col (a0) col (a0 + 2h) col (a0 + 4h) col (a0 + 6h) col (a0 + 8h) col (a0 + ah) col (a0 + ch) col (a0 + eh)
chapter 4 memory acc ess timing examples preliminary user?s manual a15555ej2v0um 130 figure 4-2. example of sdram access timing (12/14) (l) read cycle/without wait/cl = 3/sequential transfer/without page and bank change/without speculative read/local bus size: 8 bits d0 ready wait tread (1, 1, 1, 0) (0, 0, 0, 0) tlate d1 wait wait wait ready ready ready vsseq2 to vsseq0 (input) vbclk (input) busclk (output) transfer response vbdi31 to vbdi0 (output) vsbenz3 to vsbenz0 (input) vsctyp2 to vsctyp0 (input) vswrite (input) vsstz (input) vsa25 to vsa0 (input) vdcsz7 to vdcsz0 (input) cpu core ? NA85E535 a25 to a0 (output) csz7 to csz0 (output) sdrasz (output) dqm3 to dqm0 (output) bcystz (output) benz3 to benz0 (output) dc3f to dc0f (output) NA85E535 ? sdram sdwez (output) sdcasz (output) di31 to di0 (input) d2 d3 tread tread tread tread tread tread tread tread tread tread tread tread tread tread tread tlate tlate h h latency = 3 (1, 1, 1, 1) dc3r to dc0r (output) (0, 0, 0, 0) a0 a0 + 4h a0 + 8h a0 + ch (0, 1, 0) (0, 0, 0, 0) (1, 1, 1, 1) (0, 0, 1) (0, 0, 1) (0, 0, 0) t0 (0, 0, 0, 0) (0, 0, 0, 0) (0, 0, 0, 0) col (a0 + 4h) col (a0) col (a0 + 8h) col (a0 + ch) col (a0 + 1h) col (a0 + 2h) col (a0 + 3h) col (a0 + 5h) col (a0 + 6h) col (a0 + 7h) col (a0 + 9h) col (a0 + ah) col (a0 + bh) col (a0 + fh) col (a0 + dh) col (a0 + eh) d0 (a0) d0 (a0 + 1h) d0 (a0 + 2h) d0 (a0 + 3h) d1 (a0 + 4h) d1 (a0 + 5h) d1 (a0 + 6h) d1 (a0 + 7h) d2 (a0 + 8h) d2 (a0 + 9h) d2 (a0 + ah) d2 (a0 + bh) d3 (a0 + ch) d3 (a0 + dh) d3 (a0 + eh) d3 (a0 + fh)
chapter 4 memory acc ess timing examples preliminary user?s manual a15555ej2v0um 131 figure 4-2. example of sdram access timing (13/14) (m) read cycle/without wait/cl = 2/16 times of sequential transfer from speculative read hit address/local bus size: 32 bits d0 d0 wait tread col (a0) col (a0 + 4h) col (a0 + 8h) col (a0 + ch) d0 vsseq2 to vsseq0 (input) vbclk (input) busclk (output) transfer response vbdi31 to vbdi0 (output) vsbenz3 to vsbenz0 (input) vsctyp2 to vsctyp0 (input) vswrite (input) vsstz (input) vsa25 to vsa0 (input) vdcsz7 to vdcsz0 (input) cpu core ? NA85E535 a25 to a0 (output) csz7 to csz0 (output) sdrasz (output) dqm3 to dqm0 (output) bcystz (output) benz3 to benz0 (output) dc3f to dc0f (output) NA85E535 ? sdram sdwez (output) sdcasz (output) di31 to di0 (input) d3 tread tread tread tlate d1 d2 h h dc3r to dc0r (output) t0 (0, 0, 0, 0) (0, 0, 0) ready wait ready wait ready wait ready wait wait wait wait d1 d2 d7 d8 d9 d10 d11 d12 d13 d14 d15 speculative read hit tlate tlate tlate tread tread tread tread tlate tlate tread tread tread tread tlate tlate (1, 1, 1, 1) (1, 1, 1, 1) (1, 1, 1, 1) (1, 1, 1, 1) (1, 1, 1, 1) (1, 1, 1, 1) (0, 0, 0, 0) (0, 0, 0, 0) (0, 0, 0, 0) (0, 0, 0, 0) (0, 0, 0, 0) (1, 1, 1, 1) (1, 1, 1, 1) (1, 1, 1, 1) (1, 1, 1, 1) d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15 speculative read cycle speculative read cycle speculative read cycle speculative read cycle a0 a0 + 4h a0 + 8h a0 + ch a0 + 10h a0 + 14h a0 + 18h a0 + 1ch a0 + 20h a0 + 24h a0 + 28h a0 + 2ch a0 + 30h a0 + 34h a0 + 38h a0 + 3ch (1, 0, 0) d4 ready d5 d6 (0, 0, 1) ready ready (0, 0, 0, 0) (0, 0, 0, 0) (1, 1, 1, 1) (0, 0, 0, 0) (0, 0, 0, 0) (1, 1, 1, 1) (0, 0, 0, 0) (0, 0, 0, 0) (1, 1, 1, 1) (0, 0, 0, 0) (0, 0, 0, 0) (0, 0, 0, 0) (0, 0, 0, 0) (1, 1, 1, 1) (0, 0, 0, 0) ready (0, 0, 0, 0) (0, 0, 0) a0 tread tread tread tread col (a0 + 10h) col (a0 + 14h) col (a0 + 18h) col (a0 + 20h) col (a0 + 24h) col (a0 + 28h) col (a0 + 30h) col (a0 + 34h) col (a0 + 38h) col (a0 + 1ch) col (a0 + 2ch) col (a0 + 3ch)
chapter 4 memory acc ess timing examples preliminary user?s manual a15555ej2v0um 132 figure 4-2. example of sdram access timing (14/14) (n) write cycle/without wait/sequential transfer/without page and bank change/local bus size: 8 bits d0 wait tw twr (0, 0, 1) (0, 0, 1) (0, 0, 0) a0 + 4h a0 + 8h a0 + ch (0, 0, 0, 0) (1, 1, 1, 0) write command twr vsseq2 to vsseq0 (input) vbclk (input) busclk (output) transfer response vbdo31 to vbdo0 (input) vsbenz3 to vsbenz0 (input) vsctyp2 to vsctyp0 (input) vswrite (input) vsstz (input) vsa25 to vsa0 (input) vdcsz7 to vdcsz0 (input) cpu core ? NA85E535 a25 to a0 (output) csz7 to csz0 (output) sdrasz (output) dqm3 to dqm0 (output) bcystz (output) benz3 to benz0 (output) dc3f to dc0f (output) NA85E535 ? sdram sdwez (output) sdcasz (output) do31 to do0 (output) twr twr twr twr twr twr twr twr twr twr twr twr twr twr write command write command write command write command write command write command write command write command write command write command write command write command write command write command write command h (1, 1, 1, 0) dc3r to dc0r (output) (1, 1, 1, 1) a0 ready d1 d2 d3 (1, 1, 1, 0) (0, 0, 0, 0) (0, 1, 0) t0 a0 col (a0 + 4h) col (a0) col (a0 + 8h) col (a0 + ch) col (a0 + 5h) col (a0 + 6h) col (a0 + 7h) col (a0 + 9h) col (a0 + ah) col (a0 + bh) col (a0 + dh) col (a0 + eh) col (a0 + fh) col (a0 + 1h) col (a0 + 2h) col (a0 + 3h) (1, 1, 1, 1) d0 (a0 + 1h) d0 (a0 + 2h) d0 (a0 + 3h) d1 (a0 + 4h) d1 (a0 + 5h) d1 (a0 + 6h) d1 (a0 + 7h) d2 (a0 + 8h) d2 (a0 + 9h) d2 (a0 + ah) d2 (a0 + bh) d3 (a0 + ch) d3 (a0 + dh) d3 (a0 + eh) d3 (a0 + fh) d0 (a0)
chapter 4 memory acc ess timing examples preliminary user?s manual a15555ej2v0um 133 figure 4-3. example of page rom access timing (1/6) (a) without speculative read/non-sequential transfer ready d0 wait t1 t2 t1 t2 ready t1 t2 ta wait ready wait tw t1 t2 ti d1 d2 d3 t1 t2 tw ready ready d4 ahold vsseq2 to vsseq0 (input) vbclk (input) busclk (output) vsa25 to vsa0 (input) vswrite (input) vsbenz3 to vsbenz0 (input) vsctyp2 to vsctyp0 (input) vsstz (input) transfer response vbdi31 to vbdi0 (output) a25 to a0 (output) csz7 to csz0 (output) rdzf (output) wrz3 to wrz0 (output) bcystz (output) benz3 to benz0 (output) dc3r to dc0r (output) di31 to di0 (input) waitz (input) cpu core ? NA85E535 NA85E535 ? page rom vdcsz7 to vdcsz0 (input) rdzr (output) dc3f to dc0f (output) (0, 0, 0, 0) (1, 1, 1, 1) wait wait (1, 1, 1, 1) (1, 1, 1, 1) (1, 1, 1, 1) (0, 0, 0, 0) (0, 0, 0, 0) (1, 1, 1, 1) (0, 0, 0, 0) (0, 0, 0, 0) (1, 1, 1, 1) (0, 0, 0, 0) (1, 1, 1, 1) d0 d1 d3 d4 d2 t0 t0 t0 t0 t0
chapter 4 memory acc ess timing examples preliminary user?s manual a15555ej2v0um 134 figure 4-3. example of page rom access timing (2/6) (b) without speculative read/sequential transfer ready t1 t2 t1 (0, 1, 0) a0 (0, 0, 0, 0) wait a0 + 4h a0 + 8h (0, 0, 0, 0) d0 a0 a0 + 4h a0 + 8h ta t1 tw tw t2 t1 tw t2 t1 tw t2 t1 tw t2 ti wait ready wait ready ready wait ready ready ready ready vsseq2 to vsseq0 (input) vbclk (input) busclk (output) vsa25 to vsa0 (input) vswrite (input) vsbenz3 to vsbenz0 (input) vsctyp2 to vsctyp0 (input) vsstz (input) transfer response vbdi31 to vbdi0 (output) cpu core ? NA85E535 vdcsz7 to vdcsz0 (input) a25 to a0 (output) csz7 to csz0 (output) rdzf (output) wrz3 to wrz0 (output) bcystz (output) benz3 to benz0 (output) dc3r to dc0r (output) di31 to di0 (input) waitz (input) NA85E535 ? page rom rdzr (output) wrstbz (output) t2 t1 t2 t1 t2 h h dc3f to dc0f (output) (1, 1, 1, 1) (1, 1, 1, 1) (0, 0, 0, 0) a0 + 4h a0 + 8h a0 + ch (0, 0, 1) wait (0, 0, 1) (0, 1, 0) a0 (0, 0, 0, 0) wait wait a0 + ch (0, 0, 0) a0 a0 + 4h a0 + 8h a0 + ch (0, 0, 0, 0) (0, 0, 0, 0) d0 d1 d2 d3 (0, 0, 0, 0) a0 + ch (1, 1, 1, 1) (1, 1, 1, 1) (1, 1, 1, 1) (0, 0, 0, 0) d0 d1 d2 d3 d0 d1 d3 d2 d1 d2 d3 wait t0 wait ahold (0, 0, 1) t0
chapter 4 memory acc ess timing examples preliminary user?s manual a15555ej2v0um 135 figure 4-3. example of page rom access timing (3/6) (c) with speculative read/non-sequential transfer d0 ta t1 ready wait ready tw tw tw t2 t1 tw t2 t1 tw t2 t1 tw t2 d1 d2 d3 a0 a0 + 8h a0 + ch a0 + 4h vsseq2 to vsseq0 (input) vbclk (input) busclk (output) vsa25 to vsa0 (input) vswrite (input) vsbenz3 to vsbenz0 (input) vsctyp2 to vsctyp0 (input) vsstz (input) transfer response vbdi31 to vbdi0 (output) a25 to a0 (output) csz7 to csz0 (output) rdzf (output) wrz3 to wrz0 (output) bcystz (output) benz3 to benz0 (output) dc3r to dc0r (output) di31 to di0 (input) waitz (input) cpu core ? NA85E535 NA85E535 ? page rom vdcsz7 to vdcsz0 (input) rdzr (output) dc3f to dc0f (output) (0, 0, 0, 0) wait a0 + 8h a0 (0, 0, 0, 0) (1, 1, 1, 1) (1, 1, 1, 1) (1, 1, 1, 1) d2 d0 t0
chapter 4 memory acc ess timing examples preliminary user?s manual a15555ej2v0um 136 figure 4-3. example of page rom access timing (4/6) (d) with speculative read/sequential transfer d0 ta t1 ready (1, 1, 1, 1) tw tw tw t2 t1 tw t2 t1 tw t2 t1 tw t2 d1 d2 d3 a0 a0 + 8h a0 + ch a0 + 4h ready ready a0 + 4h a0 + 8h a0 + ch (0, 1, 0) (0, 0, 0) vsseq2 to vsseq0 (input) vbclk (input) busclk (output) vsa25 to vsa0 (input) vswrite (input) vsbenz3 to vsbenz0 (input) vsctyp2 to vsctyp0 (input) vsstz (input) transfer response vbdi31 to vbdi0 (output) a25 to a0 (output) csz7 to csz0 (output) rdzf (output) wrz3 to wrz0 (output) bcystz (output) benz3 to benz0 (output) dc3r to dc0r (output) di31 to di0 (input) waitz (input) cpu core ? NA85E535 NA85E535 ? page rom vdcsz7 to vdcsz0 (input) rdzr (output) (1, 1, 1, 1) dc3f to dc0f (output) wai t wai t wai t (0, 0, 1) wai t ready a0 (0, 0, 0, 0) (1, 1, 1, 1) (0, 0, 0, 0) d0 d1 d2 d3 t0
chapter 4 memory acc ess timing examples preliminary user?s manual a15555ej2v0um 137 figure 4-3. example of page rom access timing (5/6) (e) with speculative read/off-page wait = 1/without on-page/local bus size: 32 bits (1) ready d0 wai t t1 tw ready t1 tw vsseq2 to vsseq0 (input) vbclk (input) busclk (output) vsa25 to vsa0 (input) vswrite (input) vsbenz3 to vsbenz0 (input) vsctyp2 to vsctyp0 (input) vsstz (input) transfer response vbdi31 to vbdi0 (output) a25 to a0 (output) csz7 to csz0 (output) rdzf (output) wrz3 to wrz0 (output) bcystz (output) benz3 to benz0 (output) dc3r to dc0r (output) di31 to di0 (input) wai tz (input) cpu core ? NA85E535 NA85E535 ? page rom vdcsz7 to vdcsz0 (input) rdzr (output) dc3f to dc0f (output) wai t (0, 0, 0, 0) (1, 1, 1, 1) d0 d1 d3 d4 d2 t0 t2 t0 ready wai t ready wai t wai t ready wai t ready ready wai t wai t d5 d6 d7 t2 a0 a0 + 10h (1, 1, 1, 1) (0, 0, 0, 0) (1, 1, 1, 1) (0, 0, 0, 0) (0, 0, 0, 0) (1, 1, 1, 1) (0, 0, 0, 0) d4 speculative read cycle on-page address off-page cycle on-page cycle speculative read cycle off-page cycle on-page cycle a0 ready t2 t1 a0 + 4h t1 t2 a0 + 8h t1 t2 a0 + ch t1 t2 a0 + 14h t1 t2 a0 + 1ch t1 t2 a0 + 18h d1 d2 d3 d5 d6 d7 (1, 1, 1, 1) (0, 0, 0, 0) (1, 1, 1, 1) a0 + 4h a0 + 8h a0 + ch a0 + 10h a0 + 14h a0 + 18h a0 + 1ch (0, 0, 0, 0) (0, 0, 0) (1, 1, 1, 1) (1, 1, 1, 1) (0, 0, 0, 0) (1, 1, 1, 1)
chapter 4 memory acc ess timing examples preliminary user?s manual a15555ej2v0um 138 figure 4-3. example of page rom access timing (6/6) (f) with speculative read/off-page wait = 1/without on-page/local bus size: 32 bits (2) ready t1 tw vsseq2 to vsseq0 (input) vbclk (input) busclk (output) vsa25 to vsa0 (input) vswrite (input) vsbenz3 to vsbenz0 (input) vsctyp2 to vsctyp0 (input) vsstz (input) transfer response vbdi31 to vbdi0 (output) a25 to a0 (output) csz7 to csz0 (output) rdzf (output) wrz3 to wrz0 (output) bcystz (output) benz3 to benz0 (output) dc3r to dc0r (output) di31 to di0 (input) waitz (input) cpu core ? NA85E535 NA85E535 ? page rom vdcsz7 to vdcsz0 (input) rdzr (output) dc3f to dc0f (output) wait d0 d4 t0 t2 ready wait ready ready wait wait d5 d6 d7 a0 (0, 0, 0, 0) (0, 0, 0, 0) speculative read cycle on-page/off-page address off-page cycle on-page cycle t2 t1 a0 + 4h t1 t2 a0 + 8h t1 t2 a0 + ch t1 t2 a0 + 14h t1 t2 a0 + 1ch t1 t2 a0 + 18h d2 d3 d5 d6 d7 (1, 1, 1, 1) (1, 1, 1, 1) (1, 1, 1, 1) (0, 0, 0, 0) (1, 1, 1, 1) t1 t2 a0 + 10h d4 (0, 0, 0, 0) (0, 0, 0) a0 + 10h a0 + 14h a0 a0 + 18h a0 + 1ch ready wait tw (0, 0, 0, 0) (1, 1, 1, 1) (1, 1, 1, 1) d0 d1 speculative read cycle off-page cycle on-page cycle note note if successive cycles have been completed, the wait cycles set as off-page cycles are inserted regardless of whether the address to be accessed next is within or outside the page range.
chapter 4 memory acc ess timing examples preliminary user?s manual a15555ej2v0um 139 figure 4-4. example of dma transfer timing (flyby transfer (using dmac with on-chip cpu core): sram external i/o) (1/4) (a) single transfer a0 vbclk (input) busclk (output) vsa25 to vsa0 (input) vswrite (input) vsbenz3 to vsbenz0 (input) vsctyp2 to vsctyp0 (input) vsstz (input) transfer response vbdi31 to vbdi0 (output) a25 to a0 (output) csz7 to csz0 (output) rdzf (output) wrz3 to wrz0 (output) bcystz (output) benz3 to benz0 (output) dc3r to dc0r (output) di31 to di0 (input) waitz (input) cpu core ? NA85E535 NA85E535 ? sram, external i/o rdzr (output) dmactvm3 to dmactvm0 (output) dc3f to dc0f (output) dmactv3 to dmactv0 (input) dmtco3 to dmtco0 (input) dma pins vsseq2 to vsseq0 (input) dmtcom3 to dmtcom0 (output) vdcsz7 to vdcsz0 (input) iordzf (output) iordzr (output) iowrz (output) a1 a0 a0 (1, 1, 1) (1, 1, 1) (1, 1, 1) (1, 1, 1) (0, 0, 0, 0) (0, 0, 0, 0) (0, 0, 0, 0) (0, 0, 0, 0) (0, 0, 0) (0, 0, 0) (0, 0, 0) (0, 0, 0) wait wait ready ready wait ready wait ready l (0, 0, 0, 1) (0, 0, 0, 1) (0, 0, 0, 0) (0, 0, 0, 0) (0, 0, 0, 1) (0, 0, 0, 1) (0, 0, 0, 0) (0, 0, 0, 0) (0, 0, 0, 1) (0, 0, 0, 0) (0, 0, 0, 1) (0, 0, 0, 0) (0, 0, 0, 1) (0, 0, 0, 0) t1 t2 a0 t0 t0 a1 t1 t2 t1 tw a0 t0 t2 t1 tw a0 t0 tw ta t2 ti (1, 1, 1, 1) h h (0, 0, 0, 0) (0, 0, 0, 0) (0, 0, 0, 0) (1, 1, 1, 1) (1, 1, 1, 1) (0, 0, 0, 0) (1, 1, 1, 1) (1, 1, 1, 1) (1, 1, 1, 1) (1, 1, 1, 1) (0, 0, 0, 0) (1, 1, 1, 1) (0, 0, 0, 0) (1, 1, 1, 1) (0, 0, 0, 0) (1, 1, 1, 1) (0, 0, 0, 0) d0 d1 d0 d0 (0, 0, 0, 1) (0, 0, 0, 1) (0, 0, 0, 1) (0, 0, 0, 0) (0, 0, 0, 0) (0, 0, 0, 1) (0, 0, 0, 0) (0, 0, 0, 0) (0, 0, 0, 0) (0, 0, 0, 0) (0, 0, 0, 1) (0, 0, 0, 0) (0, 0, 0, 1) (0, 0, 0, 0) (0, 0, 0, 1) (0, 0, 0, 0)
chapter 4 memory acc ess timing examples preliminary user?s manual a15555ej2v0um 140 figure 4-4. example of dma transfer timing (flyby transfer (using dmac with on-chip cpu core): sram external i/o) (2/4) (b) single transfer/transfer request during speculative read speculative read cycle a0 vbclk (input) busclk (output) vsa25 to vsa0 (input) vswrite (input) vsbenz3 to vsbenz0 (input) vsctyp2 to vsctyp0 (input) vsstz (input) transfer response vbdi31 to vbdi0 (output) a25 to a0 (output) csz7 to csz0 (output) rdzf (output) wrz3 to wrz0 (output) bcystz (output) benz3 to benz0 (output) dc3r to dc0r (output) di31 to di0 (input) waitz (input) cpu core ? NA85E535 NA85E535 ? sram, external i/o rdzr (output) dmactvm3 to dmactvm0 (output) dc3f to dc0f (output) dmactv3 to dmactv0 (input) dmtco3 to dmtco0 (input) dma pins vsseq2 to vsseq0 (input) dmtcom3 to dmtcom0 (output) vdcsz7 to vdcsz0 (input) iordzf (output) iordzr (output) iowrz (output) a1 (0, 0, 0) (1, 1, 1) (0, 0, 0, 0) (0, 0, 0, 0) (0, 0, 0) (0, 0, 0) wait wait ready ready (0, 0, 0, 0) (0, 0, 0, 1) (0, 0, 0, 0) (0, 0, 0, 0) (0, 0, 0, 1) (0, 0, 0, 0) t1 t2 a0 t0 t1 t2 (1, 1, 1, 1) h h (0, 0, 0, 0) (1, 1, 1, 1) (1, 1, 1, 1) (0, 0, 0, 0) (1, 1, 1, 1) (0, 0, 0, 0) d0 d1 (0, 0, 0, 1) (0, 0, 0, 0) (0, 0, 0, 0) (0, 0, 0, 1) (0, 0, 0, 0) d0 t1 t2 t1 t2 a0 + 4h a0 + 8h a0 + ch a1 t1 t2 (1, 1, 1, 1) d2 d3 d4 (0, 0, 0, 0)
chapter 4 memory acc ess timing examples preliminary user?s manual a15555ej2v0um 141 figure 4-4. example of dma transfer timing (flyby transfer (using dmac with on-chip cpu core): sram external i/o) (3/4) (c) single transfer/division by 2 (1) a0 vbclk (input) vsa25 to vsa0 (input) vswrite (input) vsbenz3 to vsbenz0 (input) vsctyp2 to vsctyp0 (input) vsstz (input) transfer response vbdi31 to vbdi0 (output) a25 to a0 (output) csz7 to csz0 (output) rdzf (output) wrz3 to wrz0 (output) bcystz (output) benz3 to benz0 (output) dc3r to dc0r (output) di31 to di0 (input) waitz (input) cpu core ? NA85E535 NA85E535 ? sram, external i/o rdzr (output) dmactvm3 to dmactvm0 (output) dc3f to dc0f (output) dmactv3 to dmactv0 (input) dmtco3 to dmtco0 (input) dma pins vsseq2 to vsseq0 (input) dmtcom3 to dmtcom0 (output) vdcsz7 to vdcsz0 (input) iordzf (output) iordzr (output) iowrz (output) a1 (1, 1, 1) (1, 1, 1) (0, 0, 0, 0) (0, 0, 0, 0) (0, 0, 0) (0, 0, 0) wait wait ready ready (0, 0, 0, 1) (0, 0, 0, 1) (0, 0, 0, 0) (0, 0, 0, 0) (0, 0, 0, 1) (0, 0, 0, 0) a0 (1, 1, 1, 1) h h (1, 1, 1, 1) (0, 0, 0, 0) (1, 1, 1, 1) (0, 0, 0, 0) d0 (0, 0, 0, 0) (0, 0, 0, 1) (0, 0, 0, 0) a1 l busclk (output) t0 t1 t2 t0 t1 t2 (0, 0, 0, 0) (0, 0, 0, 0) (1, 1, 1, 1) (1, 1, 1, 1) (1, 1, 1, 1) d1 (0, 0, 0, 1) (0, 0, 0, 1) (0, 0, 0, 0) (0, 0, 0, 0) (0, 0, 0, 0)
chapter 4 memory acc ess timing examples preliminary user?s manual a15555ej2v0um 142 figure 4-4. example of dma transfer timing (flyby transfer (using dmac with on-chip cpu core): sram external i/o) (4/4) (d) single transfer/division by 2 (2) a0 vbclk (input) vsa25 to vsa0 (input) vswrite (input) vsbenz3 to vsbenz0 (input) vsctyp2 to vsctyp0 (input) vsstz (input) transfer response vbdi31 to vbdi0 (output) a25 to a0 (output) csz7 to csz0 (output) rdzf (output) wrz3 to wrz0 (output) bcystz (output) benz3 to benz0 (output) dc3r to dc0r (output) di31 to di0 (input) waitz (input) cpu core ? NA85E535 NA85E535 ? sram, external i/o rdzr (output) dmactvm3 to dmactvm0 (output) dc3f to dc0f (output) dmactv3 to dmactv0 (input) dmtco3 to dmtco0 (input) dma pins vsseq2 to vsseq0 (input) dmtcom3 to dmtcom0 (output) vdcsz7 to vdcsz0 (input) iordzf (output) iordzr (output) iowrz (output) a1 (1, 1, 1) (1, 1, 1) (0, 0, 0, 0) (0, 0, 0, 0) (0, 0, 0) (0, 0, 0) wait wait ready ready (0, 0, 0, 1) (0, 0, 0, 1) (0, 0, 0, 0) (0, 0, 0, 0) (0, 0, 0, 1) (0, 0, 0, 0) a0 (1, 1, 1, 1) h h (1, 1, 1, 1) (0, 0, 0, 0) (1, 1, 1, 1) (0, 0, 0, 0) d0 (0, 0, 0, 0) (0, 0, 0, 1) (0, 0, 0, 0) a1 l busclk (output) t0 (0, 0, 0, 0) (0, 0, 0, 0) (1, 1, 1, 1) (1, 1, 1, 1) (1, 1, 1, 1) d1 (0, 0, 0, 1) (0, 0, 0, 1) (0, 0, 0, 0) (0, 0, 0, 0) (0, 0, 0, 0) t0 t1 t2 t1 t2
chapter 4 memory acc ess timing examples preliminary user?s manual a15555ej2v0um 143 figure 4-5. example of dma transfer timing (flyby transfer (using dmac with on-chip cpu core): external i/o sram) (1/2) (a) single transfer a0 vbclk (input) busclk (output) vsa25 to vsa0 (input) vswrite (input) vsbenz3 to vsbenz0 (input) vsctyp2 to vsctyp0 (input) vsstz (input) transfer response vbdi31 to vbdi0 (output) a25 to a0 (output) csz7 to csz0 (output) rdzf (output) wrz3 to wrz0 (output) bcystz (output) benz3 to benz0 (output) dc3r to dc0r (output) di31 to di0 (input) waitz (input) cpu core ? NA85E535 NA85E535 ? sram, external i/o rdzr (output) dmactvm3 to dmactvm0 (output) dc3f to dc0f (output) dmactv3 to dmactv0 (input) dmtco3 to dmtco0 (input) dma pins vsseq2 to vsseq0 (input) dmtcom3 to dmtcom0 (output) vdcsz7 to vdcsz0 (input) iordzf (output) iordzr (output) iowrz (output) a1 a0 a0 (1, 1, 1) (1, 1, 1) (1, 1, 1) (1, 1, 1) (0, 0, 0, 0) (0, 0, 0, 0) (0, 0, 0, 0) (0, 0, 0, 0) (0, 0, 0) (0, 0, 0) (0, 0, 0) (0, 0, 0) wait wait ready ready wait ready wait ready l (0, 0, 0, 1) (0, 0, 0, 1) (0, 0, 0, 0) (0, 0, 0, 0) (0, 0, 0, 1) (0, 0, 0, 1) (0, 0, 0, 0) (0, 0, 0, 0) (0, 0, 0, 1) (0, 0, 0, 0) (0, 0, 0, 1) (0, 0, 0, 0) (0, 0, 0, 1) (0, 0, 0, 0) t1 t2 a0 t0 t0 a1 t1 t2 t1 tw a0 t0 t2 t1 tw a0 t0 tw ta t2 ti (0, 0, 0, 0) (0, 0, 0, 0) (0, 0, 0, 0) (1, 1, 1, 1) (1, 1, 1, 1) (0, 0, 0, 0) (1, 1, 1, 1) (1, 1, 1, 1) (1, 1, 1, 1) (1, 1, 1, 1) (0, 0, 0, 0) (1, 1, 1, 1) (0, 0, 0, 0) (1, 1, 1, 1) (0, 0, 0, 0) (1, 1, 1, 1) (0, 0, 0, 0) (0, 0, 0, 1) (0, 0, 0, 1) (0, 0, 0, 1) (0, 0, 0, 0) (0, 0, 0, 0) (0, 0, 0, 1) (0, 0, 0, 0) (0, 0, 0, 0) (0, 0, 0, 0) (0, 0, 0, 0) (0, 0, 0, 1) (0, 0, 0, 0) (0, 0, 0, 1) (0, 0, 0, 0) (0, 0, 0, 1) (0, 0, 0, 0) h h (0, 0, 0, 0) (1, 1, 1, 1) (1, 1, 1, 1) (0, 0, 0, 0) (1, 1, 1, 1) (0, 0, 0, 0) (1, 1, 1, 1) (0, 0, 0, 0) (1, 1, 1, 1) h l
chapter 4 memory acc ess timing examples preliminary user?s manual a15555ej2v0um 144 figure 4-5. example of dma transfer timing (flyby transfer (using dmac with on-chip cpu core): external i/o sram) (2/2) (b) single transfer/flyby transfer request during write a0 vbclk (input) busclk (output) vsa25 to vsa0 (input) vswrite (input) vsbenz3 to vsbenz0 (input) vsctyp2 to vsctyp0 (input) vsstz (input) transfer response vbdo31 to vbdo0 (input) a25 to a0 (output) csz7 to csz0 (output) rdzf (output) wrz3 to wrz0 (output) bcystz (output) benz3 to benz0 (output) dc3r to dc0r (output) do31 to do0 (input) wai tz (input) cpu core ? NA85E535 NA85E535 ? sram, external i/o rdzr (output) dmactvm3 to dmactvm0 (output) dc3f to dc0f (output) dmactv3 to dmactv0 (input) dmtco3 to dmtco0 (input) dma pins vsseq2 to vsseq0 (input) dmtcom3 to dmtcom0 (output) vdcsz7 to vdcsz0 (input) iordzf (output) iordzr (output) iowrz (output) a1 (0, 0, 1) (1, 1, 1) (0, 0, 0, 0) (0, 0, 0, 0) (0, 0, 1) (0, 0, 0) wai t wai t ready ready (0, 0, 0, 0) (0, 0, 0, 1) (0, 0, 0, 0) (0, 0, 0, 0) (0, 0, 0, 1) (0, 0, 0, 0) t1 t2 a0 t0 t1 a0 + 4h t2 t1 (0, 0, 0, 0) (1, 1, 1, 1) (1, 1, 1, 1) (0, 0, 0, 1) (0, 0, 0, 0) (0, 0, 0, 0) (0, 0, 0, 0) (0, 0, 0, 1) (0, 0, 0, 0) h h (0, 0, 0, 0) (1, 1, 1, 1) (1, 1, 1, 1) h a0 + 4h (0, 0, 1) (0, 0, 0, 0) (0, 0, 0) d0 d1 t2 a1 (0, 0, 0, 0) (1, 1, 1, 1) (0, 0, 0, 0) (1, 1, 1, 1) (0, 0, 0, 0) (1, 1, 1, 1) (1, 1, 1, 1) (0, 0, 0, 0) (1, 1, 1, 1) (0, 0, 0, 0) di31 to di0 (output) d2 d0 d1 l vbdi31 to vbdi0 (output)
chapter 4 memory acc ess timing examples preliminary user?s manual a15555ej2v0um 145 figure 4-6. example of dma transfer timing (flyby transfer (using dmac with on-chip cpu core): page rom external i/o (single transfer) a0 vbclk (input) busclk (output) vsa25 to vsa0 (input) vswrite (input) vsbenz3 to vsbenz0 (input) vsctyp2 to vsctyp0 (input) vsstz (input) transfer response vbdi31 to vbdi0 (output) a25 to a0 (output) csz7 to csz0 (output) rdzf (output) bcystz (output) benz3 to benz0 (output) dc3r to dc0r (output) di31 to di0 (input) waitz (input) cpu core ? NA85E535 NA85E535 ? page rom, external i/o rdzr (output) dmactvm3 to dmactvm0 (output) dc3f to dc0f (output) dmactv3 to dmactv0 (input) dmtco3 to dmtco0 (input) dma pins vsseq2 to vsseq0 (input) dmtcom3 to dmtcom0 (output) vdcsz7 to vdcsz0 (input) iordzf (output) iordzr (output) iowrz (output) a1 a0 a0 (1, 1, 1) (1, 1, 1) (1, 1, 1) (1, 1, 1) (0, 0, 0, 0) (0, 0, 0, 0) (0, 0, 0, 0) (0, 0, 0, 0) (0, 0, 0) (0, 0, 0) (0, 0, 0) (0, 0, 0) wait wait ready ready wait ready wait ready l (0, 0, 0, 1) (0, 0, 0, 1) (0, 0, 0, 0) (0, 0, 0, 0) (0, 0, 0, 1) (0, 0, 0, 1) (0, 0, 0, 0) (0, 0, 0, 0) (0, 0, 0, 1) (0, 0, 0, 0) (0, 0, 0, 1) (0, 0, 0, 0) (0, 0, 0, 1) (0, 0, 0, 0) t1 t2 a0 t0 t0 a1 t1 t2 t1 tw a0 t0 t2 t1 tw a0 t0 tw ta t2 ti h h (0, 0, 0, 0) (0, 0, 0, 0) (0, 0, 0, 0) (1, 1, 1, 1) (1, 1, 1, 1) (0, 0, 0, 0) (1, 1, 1, 1) (1, 1, 1, 1) (1, 1, 1, 1) (1, 1, 1, 1) (0, 0, 0, 0) (1, 1, 1, 1) (0, 0, 0, 0) (1, 1, 1, 1) (0, 0, 0, 0) (1, 1, 1, 1) (0, 0, 0, 0) d0 d1 d0 d0 (0, 0, 0, 1) (0, 0, 0, 1) (0, 0, 0, 1) (0, 0, 0, 0) (0, 0, 0, 0) (0, 0, 0, 1) (0, 0, 0, 0) (0, 0, 0, 0) (0, 0, 0, 0) (0, 0, 0, 0) (0, 0, 0, 1) (0, 0, 0, 0) (0, 0, 0, 1) (0, 0, 0, 0) (0, 0, 0, 1) (0, 0, 0, 0)
chapter 4 memory acc ess timing examples preliminary user?s manual a15555ej2v0um 146 figure 4-7. example of dma transfer timing (flyby transfer (using dmac with on-chip cpu core): sdram external i/o (single transfer) a0 vbclk (input) busclk (output) vsa25 to vsa0 (input) vswrite (input) vsbenz3 to vsbenz0 (input) vsctyp2 to vsctyp0 (input) vsstz (input) transfer response vbdi31 to vbdi0 (output) a25 to a0 (output) csz7 to csz0 (output) sdrasz (output) sdwez (output) bcystz (output) dqm3 to dqm0 (output) dc3r to dc0r (output) di31 to di0 (input) cpu core ? NA85E535 NA85E535 ? sdram, external i/o sdcasz (output) dmactvm3 to dmactvm0 (output) dc3f to dc0f (output) dmactv3 to dmactv0 (input) dmtco3 to dmtco0 (input) dma pins vsseq2 to vsseq0 (input) dmtcom3 to dmtcom0 (output) vdcsz7 to vdcsz0 (input) cke (output) iordzf (output) iowrz (output) (1, 1, 1) (0, 0, 0, 0) (0, 0, 0) wait ready l (0, 0, 0, 1) (0, 0, 0, 0) (0, 0, 0, 1) (0, 0, 0, 0) tact tread row t0 tf col tlate tlate h h (0, 0, 0, 0) (1, 1, 1, 1) (1, 1, 1, 1) (1, 1, 1, 1) (0, 0, 0, 0) (1, 1, 1, 1) (0, 0, 0, 1) (0, 0, 0, 0) (0, 0, 0, 0) (0, 0, 0, 0) (0, 0, 0, 1) (0, 0, 0, 0) iordzr (output) h d0 a0 (1, 1, 1) (0, 0, 0, 0) (0, 0, 0) wait ready (0, 0, 0, 1) (0, 0, 0, 0) (0, 0, 0, 1) (0, 0, 0, 0) tact tread row t0 tf col tlate tlate (0, 0, 0, 0) (1, 1, 1, 1) (0, 0, 0, 0) (1, 1, 1, 1) (0, 0, 0, 0) (0, 0, 0, 1) (0, 0, 0, 0) (0, 0, 0, 1) (0, 0, 0, 0) d0 tf ti a0 (1, 1, 1) (0, 0, 0, 0) (0, 0, 0) wait ready (0, 0, 0, 1) (0, 0, 0, 0) (0, 0, 0, 1) (0, 0, 0, 0) tread t0 tf col tlate tlate (0, 0, 0, 0) (1, 1, 1, 1) (1, 1, 1, 1) (0, 0, 0, 1) (0, 0, 0, 1) d0 tf (0, 0, 0, 0) (0, 0, 0, 0) (0, 0, 0, 0)
chapter 4 memory acc ess timing examples preliminary user?s manual a15555ej2v0um 147 figure 4-8. example of dma transfer timing (flyby transfer (using dmac with on-chip cpu core): external i/o sdram (single transfer) a0 vbclk (input) busclk (output) vsa25 to vsa0 (input) vswrite (input) vsbenz3 to vsbenz0 (input) vsctyp2 to vsctyp0 (input) vsstz (input) transfer response vbdi31 to vbdi0 (output) a25 to a0 (output) csz7 to csz0 (output) sdrasz (output) sdwez (output) bcystz (output) dqm3 to dqm0 (output) dc3r to dc0r (output) di31 to di0 (input) cpu core ? NA85E535 NA85E535 ? sdram, external i/o sdcasz (output) dmactvm3 to dmactvm0 (output) dc3f to dc0f (output) dmactv3 to dmactv0 (input) dmtco3 to dmtco0 (input) dma pins vsseq2 to vsseq0 (input) dmtcom3 to dmtcom0 (output) vdcsz7 to vdcsz0 (input) cke (output) iordzf (output) iowrz (output) (1, 1, 1) (0, 0, 0, 0) (0, 0, 0) wait ready l (0, 0, 0, 1) (0, 0, 0, 0) (0, 0, 0, 1) (0, 0, 0, 0) tact tf row t0 twr col h (0, 0, 0, 0) (1, 1, 1, 1) (1, 1, 1, 1) (0, 0, 0, 0) (1, 1, 1, 1) (0, 0, 0, 1) (0, 0, 0, 0) (0, 0, 0, 0) (0, 0, 0, 0) (0, 0, 0, 1) (0, 0, 0, 0) iordzr (output) d0 (0, 0, 0, 0) h (1, 1, 1, 1) a0 (1, 1, 1) (0, 0, 0, 0) (0, 0, 0) wait ready (0, 0, 0, 1) (0, 0, 0, 0) (0, 0, 0, 1) (0, 0, 0, 0) tact tf row t0 twr col (0, 0, 0, 0) (1, 1, 1, 1) (1, 1, 1, 1) (0, 0, 0, 1) (0, 0, 0, 0) (0, 0, 0, 1) (0, 0, 0, 0) d0 (0, 0, 0, 0) tf tf a0 (1, 1, 1) (0, 0, 0, 0) (0, 0, 0) wait ready (0, 0, 0, 1) (0, 0, 0, 0) (0, 0, 0, 1) (0, 0, 0, 0) tf t0 twr col (0, 0, 0, 0) (1, 1, 1, 1) (0, 0, 0, 0) (1, 1, 1, 1) (0, 0, 0, 1) (0, 0, 0, 0) (0, 0, 0, 1) (0, 0, 0, 0) d0 a0 (1, 1, 1) (0, 0, 0, 0) (0, 0, 0) wait ready (0, 0, 0, 1) (0, 0, 0, 0) (0, 0, 0, 1) (0, 0, 0, 0) ti tf t0 twr col (0, 0, 0, 0) (1, 1, 1, 1) (0, 0, 0, 0) (1, 1, 1, 1) (0, 0, 0, 1) (0, 0, 0, 0) (0, 0, 0, 1) (0, 0, 0, 0) d0
chapter 4 memory acc ess timing examples preliminary user?s manual a15555ej2v0um 148 figure 4-9. example of dma transfer timing (flyby transfer (with na85e300): sram external i/o) (1/2) (a) single transfer a0 vbclk (input) busclk (output) vsa25 to vsa0 (input) vswrite (input) vsbenz3 to vsbenz0 (input) vsctyp2 to vsctyp0 (input) vsstz (input) transfer response vbdi31 to vbdi0 (output) a25 to a0 (output) csz7 to csz0 (output) rdzf (output) wrz3 to wrz0 (output) bcystz (output) benz3 to benz0 (output) dc3r to dc0r (output) di31 to di0 (input) waitz (input) cpu core ? NA85E535 NA85E535 ? sram, external i/o rdzr (output) dmxczm03 to dmxczm00 (output) dc3f to dc0f (output) dmxcsz03 to dmxcsz00 (input) dmxtco03 to dmxtco00 (input) dma pins vsseq2 to vsseq0 (input) dmxtcm03 to dmxtcm00 (output) vdcsz7 to vdcsz0 (input) iordzf (output) iordzr (output) iowrz (output) a1 (1, 1, 1) (1, 1, 1) (0, 0, 0, 0) (0, 0, 0, 0) (0, 0, 0) (0, 0, 0) wait wait ready ready l (1, 1, 1, 0) (1, 1, 1, 0) (1, 1, 1, 1) (0, 0, 0, 0) (0, 0, 0, 1) (0, 0, 0, 0) t1 t2 a0 t0 t0 a1 t1 t2 h h (0, 0, 0, 0) (1, 1, 1, 1) (1, 1, 1, 1) (0, 0, 0, 0) (0, 0, 0, 0) (1, 1, 1, 1) d0 d1 (1, 1, 1, 0) (1, 1, 1, 1) (1, 1, 1, 1) (1, 1, 1, 0) (0, 0, 0, 0) (0, 0, 0, 1) (1, 1, 1, 1) (1, 1, 1, 1) (1, 1, 1, 1) (0, 0, 0, 0) (1, 1, 1, 1) (0, 0, 0, 0)
chapter 4 memory acc ess timing examples preliminary user?s manual a15555ej2v0um 149 figure 4-9. example of dma transfer timing (flyby transfer (with na85e300): sram external i/o) (2/2) (b) single transfer (4 words) vbclk (input) busclk (output) vsa25 to vsa0 (input) vswrite (input) vsbenz3 to vsbenz0 (input) vsctyp2 to vsctyp0 (input) vsstz (input) transfer response vbdi31 to vbdi0 (output) a25 to a0 (output) csz7 to csz0 (output) rdzf (output) wrz3 to wrz0 (output) bcystz (output) benz3 to benz0 (output) dc3r to dc0r (output) di31 to di0 (input) waitz (input) cpu core ? NA85E535 NA85E535 ? sram, external i/o rdzr (output) dmxczm03 to dmxczm00 (output) dc3f to dc0f (output) dmxcsz03 to dmxcsz00 (input) dmxtco03 to dmxtco00 (input) dma pins vsseq2 to vsseq0 (input) dmxtcm03 to dmxtcm00 (output) vdcsz7 to vdcsz0 (input) iordzf (output) iordzr (output) iowrz (output) a0 a0 + 4h wait wait ready l (1, 1, 1, 0) (1, 1, 1, 0) (0, 0, 0, 0) t1 t2 a0 t0 a0 + 4h t1 t2 h h (0, 0, 0, 0) (1, 1, 1, 1) (0, 0, 0, 0) (1, 1, 1, 1) d0 d1 (1, 1, 1, 1) (1, 1, 1, 1) (1, 1, 1, 1) (0, 0, 0, 0) (0, 0, 0, 1) (1, 1, 1, 1) (1, 1, 1, 1) (1, 1, 1, 1) (0, 0, 0, 0) (0, 0, 0, 0) a0 + 8h a0 + ch a0 a0 + 4h a0 + 8h a0 + ch (1, 1, 1) (1, 1, 1) (1, 1, 1) (1, 1, 1) (1, 1, 1) (1, 1, 1) (1, 1, 1) (1, 1, 1) (0, 0, 0, 0) (0, 0, 0, 0) (0, 0, 0, 0) (0, 0, 0, 0) (0, 0, 0, 0) (0, 0, 0, 0) (0, 0, 0, 0) (0, 0, 0, 0) (0, 1, 0) (0, 0, 1) (0, 0, 1) (0, 0, 0) (0, 1, 0) (0, 0, 1) (0, 0, 1) (0, 0, 0) ready wait ready wait ready wait ready wait ready wait ready wait ready (1, 1, 1, 0) (1, 1, 1, 0) (1, 1, 1, 1) (1, 1, 1, 0) (1, 1, 1, 0) (1, 1, 1, 0) (1, 1, 1, 0) (1, 1, 1, 1) (0, 0, 0, 1) (0, 0, 0, 1) (0, 0, 0, 0) a0 + 8h t2 t1 a0 + ch t2 t1 t0 a0 ta t1 tw t2 ti ta t1 tw t2 ti a0 + 4h ta t1 tw t2 ti a0 + 8h ta t1 tw t2 ti a0 + ch (0, 0, 0, 0) (1, 1, 1, 1) (1, 1, 1, 1) (0, 0, 0, 0) d2 d3 d0 d1 d2 d3 (1, 1, 1, 0) (1, 1, 1, 1) (0, 0, 0, 1) (0, 0, 0, 0)
chapter 4 memory acc ess timing examples preliminary user?s manual a15555ej2v0um 150 figure 4-10. example of dma transfer timing (flyby transfer (with na85e300): external i/o sram) (1/2) (a) single transfer a0 vbclk (input) busclk (output) vsa25 to vsa0 (input) vswrite (input) vsbenz3 to vsbenz0 (input) vsctyp2 to vsctyp0 (input) vsstz (input) transfer response vbdi31 to vbdi0 (output) a25 to a0 (output) csz7 to csz0 (output) rdzf (output) wrz3 to wrz0 (output) bcystz (output) benz3 to benz0 (output) dc3r to dc0r (output) di31 to di0 (input) waitz (input) cpu core ? NA85E535 NA85E535 ? sram, external i/o rdzr (output) dmxczm03 to dmxczm00 (output) dc3f to dc0f (output) dmxcsz03 to dmxcsz00 (input) dmxtco03 to dmxtco00 (input) dma pins vsseq2 to vsseq0 (input) dmxtcm03 to dmxtcm00 (output) vdcsz7 to vdcsz0 (input) iordzf (output) iordzr (output) iowrz (output) a1 (1, 1, 1) (1, 1, 1) (0, 0, 0, 0) (0, 0, 0, 0) (0, 0, 0) (0, 0, 0) wait wait ready ready l (1, 1, 1, 0) (1, 1, 1, 0) (1, 1, 1, 1) (0, 0, 0, 0) (0, 0, 0, 1) (0, 0, 0, 0) t1 t2 a0 t0 t0 a1 t1 t2 h h (0, 0, 0, 0) (1, 1, 1, 1) (1, 1, 1, 1) (0, 0, 0, 0) (0, 0, 0, 0) (1, 1, 1, 1) (1, 1, 1, 0) (1, 1, 1, 1) (1, 1, 1, 1) (1, 1, 1, 0) (0, 0, 0, 0) (0, 0, 0, 1) (1, 1, 1, 1) (1, 1, 1, 1) (1, 1, 1, 1) (0, 0, 0, 0) (1, 1, 1, 1) (0, 0, 0, 0) (0, 0, 0, 0) (1, 1, 1, 1) (0, 0, 0, 0) (1, 1, 1, 1) h d0 d1
chapter 4 memory acc ess timing examples preliminary user?s manual a15555ej2v0um 151 figure 4-10. example of dma transfer timing (flyby transfer (with na85e300): external i/o sram) (2/2) (b) single transfer (4 words) vbclk (input) busclk (output) vsa25 to vsa0 (input) vswrite (input) vsbenz3 to vsbenz0 (input) vsctyp2 to vsctyp0 (input) vsstz (input) transfer response vbdi31 to vbdi0 (output) a25 to a0 (output) csz7 to csz0 (output) rdzf (output) wrz3 to wrz0 (output) bcystz (output) benz3 to benz0 (output) dc3r to dc0r (output) di31 to di0 (input) waitz (input) cpu core ? NA85E535 NA85E535 ? sram, external i/o rdzr (output) dmxczm03 to dmxczm00 (output) dc3f to dc0f (output) dmxcsz03 to dmxcsz00 (input) dmxtco03 to dmxtco00 (input) dma pins vsseq2 to vsseq0 (input) dmxtcm03 to dmxtcm00 (output) vdcsz7 to vdcsz0 (input) iordzf (output) iordzr (output) iowrz (output) a0 a0 + 4h wait wait ready l (1, 1, 1, 0) (1, 1, 1, 0) (0, 0, 0, 0) t1 t2 a0 t0 a0 + 4h t1 t2 (0, 0, 0, 0) (1, 1, 1, 1) (0, 0, 0, 0) (1, 1, 1, 1) d0 d1 (1, 1, 1, 0) (1, 1, 1, 1) (1, 1, 1, 1) (0, 0, 0, 0) (0, 0, 0, 1) (1, 1, 1, 1) (1, 1, 1, 1) (0, 0, 0, 0) (0, 0, 0, 0) a0 + 8h a0 + ch a0 a0 + 4h a0 + 8h a0 + ch (1, 1, 1) (1, 1, 1) (1, 1, 1) (1, 1, 1) (1, 1, 1) (1, 1, 1) (1, 1, 1) (1, 1, 1) (0, 0, 0, 0) (0, 0, 0, 0) (0, 0, 0, 0) (0, 0, 0, 0) (0, 0, 0, 0) (0, 0, 0, 0) (0, 0, 0, 0) (0, 0, 0, 0) (0, 1, 0) (0, 0, 1) (0, 0, 1) (0, 0, 0) (0, 1, 0) (0, 0, 1) (0, 0, 1) (0, 0, 0) ready wait ready wait ready wait ready wait ready wait ready wait ready (1, 1, 1, 0) (1, 1, 1, 0) (1, 1, 1, 1) (1, 1, 1, 0) (1, 1, 1, 0) (1, 1, 1, 0) (1, 1, 1, 0) (1, 1, 1, 1) (0, 0, 0, 1) (0, 0, 0, 1) (0, 0, 0, 0) a0 + 8h t2 t1 a0 + ch t2 t1 t0 a0 ta t1 tw t2 ti ta t1 tw t2 ti a0 + 4h ta t1 tw t2 ti a0 + 8h ta t1 tw t2 ti a0 + ch (0, 0, 0, 0) (1, 1, 1, 1) (1, 1, 1, 1) (0, 0, 0, 0) d2 d3 d0 d1 d2 d3 (1, 1, 1, 0) (1, 1, 1, 1) (0, 0, 0, 1) (0, 0, 0, 0) h h h (0, 0, 0, 0) (1, 1, 1, 1) (1, 1, 1, 1) (0, 0, 0, 0) (1, 1, 1, 1) (0, 0, 0, 0) (1, 1, 1, 1) (0, 0, 0, 0) (1, 1, 1, 1) (0, 0, 0, 0) (1, 1, 1, 1) (0, 0, 0, 0) (1, 1, 1, 1) (0, 0, 0, 0) (1, 1, 1, 1) (0, 0, 0, 0) (1, 1, 1, 1)
chapter 4 memory acc ess timing examples preliminary user?s manual a15555ej2v0um 152 figure 4-11. example of dma transfer timing (flyby transfer (with na85e300): page rom external i/o) (single transfer (4 words))) vbclk (i nput) busclk (output) vsa25 to vsa0 (input) vswrite (input) vsbenz3 to vsbenz0 (input) vsctyp2 to vsctyp0 (input) vsstz (input) transfer response vbdi31 t o vbdi0 (output) a25 to a0 (output) csz7 to csz0 (output) rdzf (output) bcystz (output) benz3 to benz0 (output) dc3r to dc0r (output) di31 to di0 (input) waitz (input) cpu core ? NA85E535 NA85E535 ? page rom, external i/o rdzr (output) dmxczm03 to dmxczm00 (output) dc3f to dc0f (output) dmxcsz03 to dmxcsz00 (input) dmxtco03 to dmxtco00 (input) dma pins vsseq2 to vsseq0 (input) dmxtcm03 to dmxtcm00 (output) vdcsz7 t o vdcsz0 (input) iordzf (output) iordzr (output) iowrz (output) a0 a0 + 4h wai t wai t ready l (1, 1, 1, 0) (1, 1, 1, 0) (0, 0, 0, 0) t1 t2 a0 t0 a0 + 4h t1 t2 h h (0, 0, 0, 0) (1, 1, 1, 1) (0, 0, 0, 0) (1, 1, 1, 1) d0 d1 (1, 1, 1, 0) (1, 1, 1, 1) (1, 1, 1, 1) (0, 0, 0, 0) (0, 0, 0, 1) (1, 1, 1, 1) (1, 1, 1, 1) (0, 0, 0, 0) (0, 0, 0, 0) a0 + 8h a0 + ch a0 a0 + 4h a0 + 8h a0 + ch (1, 1, 1) (1, 1, 1) (1, 1, 1) (1, 1, 1) (1, 1, 1) (1, 1, 1) (1, 1, 1) (1, 1, 1) (0, 0, 0, 0) (0, 0, 0, 0) (0, 0, 0, 0) (0, 0, 0, 0) (0, 0, 0, 0) (0, 0, 0, 0) (0, 0, 0, 0) (0, 0, 0, 0) (0, 1, 0) (0, 0, 1) (0, 0, 1) (0, 0, 0) (0, 1, 0) (0, 0, 1) (0, 0, 1) (0, 0, 0) ready wai t ready wai t ready wai t ready wai t ready wai t ready wai t ready (1, 1, 1, 0) (1, 1, 1, 0) (1, 1, 1, 1) (1, 1, 1, 0) (1, 1, 1, 0) (1, 1, 1, 0) (1, 1, 1, 0) (1, 1, 1, 1) (0, 0, 0, 1) (0, 0, 0, 1) (0, 0, 0, 0) a0 + 8h t2 t1 a0 + ch t2 t1 t0 a0 ta t1 tw t2 t1 tw t2 a0 + 4h ti a0 + 8h t1 tw t2 a0 + ch (0, 0, 0, 0) (1, 1, 1, 1) (1, 1, 1, 1) (0, 0, 0, 0) d2 d3 d0 (1, 1, 1, 0) (1, 1, 1, 1) (0, 0, 0, 1) (0, 0, 0, 0) tw t1 tw t2 d1 d2 d3
chapter 4 memory acc ess timing examples preliminary user?s manual a15555ej2v0um 153 figure 4-12. example of dma transfer timing (flyby transfer (with na85e300): sdram external i/o) (single transfer (4 words))) vbclk (input) busclk (output) vsa25 to vsa0 (input) vswrite (input) vsbenz3 to vsbenz0 (input) vsctyp2 to vsctyp0 (input) vsstz (input) transfer response vbdi31 to vbdi0 (output) a25 to a0 (output) csz7 to csz0 (output) bcystz (output) dqm3 to dqm0 (output) dc3r to dc0r (output) di31 to di0 (input) cpu core ? NA85E535 NA85E535 ? sdram, external i/o dmxczm03 to dmxczm00 (output) dc3f to dc0f (output) dmxcsz03 to dmxcsz00 (input) dmxtco03 to dmxtco00 (input) dma pins vsseq2 to vsseq0 (input) dmxtcm03 to dmxtcm00 (output) vdcsz7 to vdcsz0 (input) iordzf (output) iordzr (output) iowrz (output) a0 a0 + 4h wait wait ready l (1, 1, 1, 0) (1, 1, 1, 0) (0, 0, 0, 0) tact tread row t0 col (a0) tf tread h h (0, 0, 0, 0) (1, 1, 1, 1) (0, 0, 0, 0) (1, 1, 1, 1) d0 d1 (0, 0, 0, 1) (0, 0, 0, 0) (0, 0, 0, 0) (0, 0, 0, 0) (0, 0, 0, 1) (1, 1, 1, 1) (1, 1, 1, 1) (0, 0, 0, 0) (0, 0, 0, 0) a0 + 8h a0 + ch a0 (1, 1, 1) (1, 1, 1) (1, 1, 1) (1, 1, 1) (1, 1, 1) (0, 0, 0, 0) (0, 0, 0, 0) (0, 0, 0, 0) (0, 0, 0, 0) (0, 0, 0, 0) (0, 1, 0) (0, 1, 0) (0, 1, 0) (0, 0, 0) (0, 1, 0) ready wait ready wait ready wait (1, 1, 1, 0) (1, 1, 1, 0) (1, 1, 1, 1) (1, 1, 1, 0) (0, 0, 0, 1) (1, 1, 1, 0) col (a0 + 4h) tread tf col (a0 + 8h) tf d2 d3 a0 + 4h a0 + 8h a0 + ch (1, 1, 1) (1, 1, 1) (0, 0, 0, 0) (0, 0, 0, 0) (0, 1, 0) (0, 1, 0) (1, 1, 1) (0, 0, 0, 0) (0, 0, 0) wait ready ready wait ready wait ready (1, 1, 1, 0) (1, 1, 1, 0) (1, 1, 1, 0) (1, 1, 1, 1) (0, 0, 0, 0) tread tf tlate tlate tread t0 tf tread tread tf tf tread tf tlate tlate col (a0 + ch) col (a0) col (a0 + 4h) col (a0 + 8h) col (a0 + ch) sdrasz (output) sdcasz (output) sdwez (output) cke (output) h (0, 0, 0, 0) (1, 1, 1, 1) (1, 1, 1, 1) (0, 0, 0, 0) d0 d1 d2 d3 (0, 0, 0, 1) (0, 0, 0, 0) (0, 0, 0, 1) (0, 0, 0, 0)
chapter 4 memory acc ess timing examples preliminary user?s manual a15555ej2v0um 154 figure 4-13. example of dma transfer timing (flyby transfer (with na85e300): external i/o sdram) (single transfer (4 words))) vbclk (input) busclk (output) vsa25 to vsa0 (input) vswrite (input) vsbenz3 to vsbenz0 (input) vsctyp2 to vsctyp0 (input) vsstz (input) transfer response vbdi31 to vbdi0 (output) a25 to a0 (output) csz7 t o csz0 (output) bcystz (output) dqm3 t o dqm0 (output) dc3r to dc0r (output) di31 to di0 (input) cpu core ? NA85E535 NA85E535 ? sdram, external i/o dmxczm03 to dmxczm00 (output) dc3f to dc0f (output) dmxcsz03 to dmxcsz00 (input) dmxtco03 to dmxtco00 (input) dma pins vsseq2 to vsseq0 (input) dmxtcm03 to dmxtcm00 (output) vdcsz7 t o vdcsz0 (input) iordzf (output) iordzr (output) iowrz (output) a0 a0 + 4h wait wait ready l (1, 1, 1, 0) (1, 1, 1, 0) (0, 0, 0, 0) tact row t0 col (a0) twr tf (1, 1, 1, 1) (0, 0, 0, 0) (1, 1, 1, 1) d0 d1 (0, 0, 0, 1) (0, 0, 0, 0) (0, 0, 0, 0) (0, 0, 0, 0) (0, 0, 0, 1) (1, 1, 1, 1) (1, 1, 1, 1) (0, 0, 0, 0) (0, 0, 0, 0) a0 + 8h a0 + ch a0 (1, 1, 1) (1, 1, 1) (1, 1, 1) (1, 1, 1) (1, 1, 1) (0, 0, 0, 0) (0, 0, 0, 0) (0, 0, 0, 0) (0, 0, 0, 0) (0, 0, 0, 0) (0, 1, 0) (0, 0, 1) (0, 0, 1) (0, 0, 0) (0, 1, 0) ready wait ready wait ready wait (1, 1, 1, 0) (1, 1, 1, 0) (1, 1, 1, 1) (1, 1, 1, 0) (0, 0, 0, 1) (0, 0, 0, 1) col (a0 + 4h) tf twr col (a0 + 8h) twr d2 d3 a0 + 4h a0 + 8h a0 + ch (1, 1, 1) (1, 1, 1) (0, 0, 0, 0) (0, 0, 0, 0) (0, 0, 1) (0, 0, 1) (1, 1, 1) (0, 0, 0, 0) (0, 0, 0) wait ready ready wait ready wait ready (1, 1, 1, 0) (1, 1, 1, 0) (1, 1, 1, 0) (1, 1, 1, 1) (0, 0, 0, 0) tf twr t0 tf twr twr tf tf twr tf col (a0 + ch) col (a0) col (a0 + 4h) col (a0 + 8h) col (a0 + ch) sdrasz (output) sdcasz (output) sdwez (output) cke (output) (1, 1, 1, 1) (0, 0, 0, 0) (0, 0, 0, 1) (0, 0, 0, 0) (0, 0, 0, 1) (0, 0, 0, 0) tf h h (0, 0, 0, 0) (0, 0, 0, 0) (0, 0, 0, 0) (0, 0, 0, 0) twr (0, 0, 0, 0) (0, 0, 0, 0) (0, 0, 0, 0) (0, 0, 0, 0) (1, 1, 1, 1) d0 d1 d2 d3
chapter 4 memory acc ess timing examples preliminary user?s manual a15555ej2v0um 155 figure 4-14. example of dma transfer timing (2-cycle transfer (using dmac with on-chip cpu core): sram sram) (1/5) (a) single transfer/without wait/without speculative read/local bus size: 32 bits sa0 (0, 0, 0, 1) (0, 0, 0, 0) (0, 0, 0, 0) (0, 0, 0, 0) d0 (1, 1, 1, 1) (1, 1, 1, 1) (0, 0, 0, 0) (0, 0, 0, 0) (0, 0, 0, 0) d0 (0, 0, 0, 0) sa0 da0 (1, 1, 1, 1) (1, 1, 1, 1) (0, 0, 0, 0) (1, 1, 1, 1) (0, 0, 0, 0) (1, 1, 1, 1) sa0 da0 (0, 0, 0, 0) (1, 1, 1, 1) (1, 1, 1, 1) (1, 1, 1, 1) (0, 0, 0, 0) (1, 1, 1, 1) (0, 0, 0, 0) (1, 1, 1, 1) (0, 0, 0, 0) (1, 1, 1, 1) (1, 1, 1, 1) (0, 0, 0, 0) d0 d0 (1, 1, 0) (1, 1, 0) (0, 0, 0, 0) (0, 0, 0, 0) (0, 0, 0) (0, 0, 0) wait wait ready ready d0 da0 d0 (0, 0, 0, 1) (0, 0, 0, 0) (0, 0, 0, 1) (0, 0, 0, 0) (0, 0, 0, 1) (0, 0, 0, 0) wait ready d0 wait ready d0 (0, 0, 0, 1) (0, 0, 0, 0) (0, 0, 0, 1) (0, 0, 0, 0) (0, 0, 0, 0) (1, 1, 0) (1, 1, 0) (0, 0, 0, 0) (0, 0, 0, 0) (0, 0, 0) (0, 0, 0) sa0 da0 t1 t2 t1 t2 vbclk (input) busclk (output) vsa25 to vsa0 (input) vsbenz3 to vsbenz0 (input) vsctyp2 to vsctyp0 (input) vsstz (input) transfer response vbdi31 to vbdi0 (output) a25 to a0 (output) csz7 to csz0 (output) rdzf (output) wrz3 to wrz0 (output) bcystz (output) benz3 to benz0 (output) dc3r to dc0r (output) di31 to di0 (input) do31 to do0 (output) cpu core ? NA85E535 NA85E535 ? sram vdcsz7 to vdcsz0 (input) rdzr (output) vbdo31 to vbdo0 (input) dmactvm3 to dmactvm0 (output) dc3f to dc0f (output) dmactv3 to dmactv0 (input) dmtco3 to dmtco0 (input) dma pins vsseq2 to vsseq0 (input) t1 t2 t1 t2 dmtcom3 to dmtcom0 (output) vswrite (input)
chapter 4 memory acc ess timing examples preliminary user?s manual a15555ej2v0um 156 figure 4-14. example of dma transfer timing (2-cycle transfer (using dmac with on-chip cpu core): sram sram) (2/5) (b) block transfer/with speculative read/local bus size: 32 bits da0 + 4h (0, 0, 0, 0) (1, 1, 1, 1) (1, 1, 1, 1) (1, 1, 1, 1) (0, 0, 0, 0) d0 (1, 1, 1, 1) (0, 0, 0, 0) (0, 0, 0, 0) d0 (0, 0, 0, 0) sa0 sa0 + 8h da0 da0 + 8h (1, 1, 1, 1) (1, 1, 1, 1) (0, 0, 0, 0) (1, 1, 1, 1) (0, 0, 0, 0) d2 (0, 0, 0, 0) (0, 0, 0, 1) (0, 0, 0, 0) sa0 + 4h sa0 + ch da0 + ch (1, 1, 1, 1) (0, 0, 0, 0) (0, 0, 0, 0) (1, 1, 1, 1) (0, 0, 0, 0) (1, 1, 1, 1) (0, 0, 0, 0) (1, 1, 1, 1) (0, 0, 0, 0) (1, 1, 1, 1) (0, 0, 0, 0) d1 d2 d3 d1 d3 ready da0 + ch (1, 1, 0) (0, 0, 0, 0) (0, 0, 0) wait d3 (0, 0, 0, 1) (0, 0, 0, 0) (0, 0, 0, 1) (0, 0, 0, 0) sa0 + 8h sa0 + ch da0 + 8h (1, 1, 0) (0, 0, 0, 0) (0, 0, 0) (1, 1, 0) (0, 0, 0, 0) (0, 0, 0) (1, 1, 0) (0, 0, 0, 0) (0, 0, 0) ready wait ready wait ready wait ready d2 d3 d1 d2 (0, 0, 0, 0) (0, 0, 0, 1) (0, 0, 0, 0) (0, 0, 0, 1) (0, 0, 0, 0) (0, 0, 0, 1) (0, 0, 0, 0) wait ready d0 wait ready d0 (0, 0, 0, 1) (0, 0, 0, 0) (0, 0, 0, 1) (0, 0, 0, 0) (0, 0, 0, 0) sa0 da0 (1, 1, 0) (1, 1, 0) (0, 0, 0, 0) (0, 0, 0, 0) (0, 0, 0) (0, 0, 0) d1 sa0 + 4h da0 + 4h (1, 1, 0) (0, 0, 0, 0) (0, 0, 0) (1, 1, 0) (0, 0, 0, 0) (0, 0, 0) wait ready wait (0, 0, 0, 1) (0, 0, 0, 0) (0, 0, 0, 1) t1 t2 t1 t2 vbclk (input) busclk (output) vsa25 to vsa0 (input) vswrite (input) vsbenz3 to vsbenz0 (input) vsctyp2 to vsctyp0 (input) vsstz (input) transfer response vbdi31 to vbdi0 (output) a25 to a0 (output) csz7 to csz0 (output) rdzf (output) wrz3 to wrz0 (output) bcystz (output) benz3 to benz0 (output) dc3r to dc0r (output) di31 to di0 (input) do31 to do0 (output) cpu core ? NA85E535 NA85E535 ? sram rdzr (output) vbdo31 to vbdo0 (input) dmactvm3 to dmactvm0 (output) dc3f to dc0f (output) dmactv3 to dmactv0 (input) dmtco3 to dmtco0 (input) dma pins vsseq2 to vsseq0 (input) t1 t2 t1 t2 dmtcom3 to dmtcom0 (output) t1 t2 t1 t2 t1 t2 t1 t2 vdcsz7 to vdcsz0 (input) (1, 1, 1, 1) (1, 1, 1, 1)
chapter 4 memory acc ess timing examples preliminary user?s manual a15555ej2v0um 157 figure 4-14. example of dma transfer timing (2-cycle transfer (using dmac with on-chip cpu core): sram sram) (3/5) (c) block transfer/without speculative read/local bus size: 32 bits (0, 0, 0, 0) (1, 1, 1, 1) (1, 1, 1, 1) (1, 1, 1, 1) (0, 0, 0, 0) d0 (1, 1, 1, 1) (0, 0, 0, 0) (0, 0, 0, 0) d0 (0, 0, 0, 0) sa0 sa0 + 4h sa0 + 8h sa0 + ch (1, 1, 1, 1) (1, 1, 1, 1) (0, 0, 0, 0) (1, 1, 1, 1) (0, 0, 0, 0) d2 (0, 0, 0, 0) (0, 0, 0, 1) (0, 0, 0, 0) da0 da0 + 4h da0 + 8h da0 + ch (1, 1, 1, 1) (0, 0, 0, 0) (0, 0, 0, 0) (1, 1, 1, 1) (0, 0, 0, 0) (1, 1, 1, 1) (0, 0, 0, 0) (1, 1, 1, 1) (0, 0, 0, 0) (1, 1, 1, 1) (0, 0, 0, 0) d1 d2 d3 d1 d3 (0, 0, 0, 0) (0, 0, 0, 0) (0, 0, 0, 0) (1, 1, 1, 1) (1, 1, 1, 1) (0, 0, 0, 0) (0, 0, 0, 0) (0, 0, 0, 0) (1, 1, 1, 1) (0, 0, 0, 0) (1, 1, 1, 1) (0, 0, 0, 0) (1, 1, 1, 1) (1, 1, 1, 1) (0, 0, 0, 0) ready wai t ready d0 wai t ready d0 (0, 0, 0, 1) (0, 0, 0, 0) (0, 0, 0, 1) (0, 0, 0, 0) (0, 0, 0, 0) sa0 da0 sa0 + 8h (1, 1, 0) (1, 1, 0) (0, 0, 0, 0) (0, 0, 0, 0) (0, 0, 0) (0, 0, 0) d1 sa0 + 4h da0 + 4h sa0 + ch da0 + 8h da0 + ch (1, 1, 0) (0, 0, 0, 0) (0, 0, 0) (1, 1, 0) (0, 0, 0, 0) (0, 0, 0) (1, 1, 0) (0, 0, 0, 0) (0, 0, 0) (1, 1, 0) (0, 0, 0, 0) (0, 0, 0) (1, 1, 0) (0, 0, 0, 0) (0, 0, 0) (1, 1, 0) (0, 0, 0, 0) (0, 0, 0) wai t ready wai t ready wai t ready wai t ready wai t ready wai t d2 d3 d1 d2 d3 (0, 0, 0, 1) (0, 0, 0, 0) (0, 0, 0, 1) (0, 0, 0, 0) (0, 0, 0, 1) (0, 0, 0, 0) (0, 0, 0, 1) (0, 0, 0, 0) (0, 0, 0, 1) (0, 0, 0, 0) (0, 0, 0, 1) (0, 0, 0, 0) (0, 0, 0, 1) (0, 0, 0, 0) t1 t2 t1 t2 vbclk (input) busclk (out put) vsa25 to vsa0 (input) vswrite (input) vsbenz3 t o vsbenz0 (input) vsctyp2 t o vsctyp0 (input) vsstz (input) transfer response vbdi 31 t o vbdi 0 (output) a25 to a0 (output) csz7 to csz0 (output) rdzf (output) wrz3 t o wrz0 (output) bcystz (output) benz3 t o benz0 (output) dc3r to dc0r (output) di 31 t o di 0 (input) do31 t o do0 (output) cpu core ? NA85E535 NA85E535 ? sram rdzr (output) vbdo31 t o vbdo0 (input) dmactvm3 to dmactvm0 (output) dc3f to dc0f (output) dmactv3 t o dmactv0 (input) dmtco3 to dmtco0 (input) dma pi ns vsseq2 to vsseq0 (input) t1 t2 t1 t2 dmtcom3 to dmtcom0 (output) t1 t2 t1 t2 t1 t2 t1 t2 vdcsz7 to vdcsz0 (input) (1, 1, 1, 1) (1, 1, 1, 1)
chapter 4 memory acc ess timing examples preliminary user?s manual a15555ej2v0um 158 figure 4-14. example of dma transfer timing (2-cycle transfer (using dmac with on-chip cpu core): sram sram) (4/5) (d) line transfer/with speculative read/local bus size: 32 bits (0, 0, 0, 0) (1, 1, 1, 1) (1, 1, 1, 1) (1, 1, 1, 1) (0, 0, 0, 0) d0 (1, 1, 1, 1) (0, 0, 0, 0) (0, 0, 0, 0) d0 (0, 0, 0, 0) sa0 sa0 + 8h da0 + 4h da0 + 8h (1, 1, 1, 1) (1, 1, 1, 1) (0, 0, 0, 0) (1, 1, 1, 1) d2 (0, 0, 0, 0) (0, 0, 0, 1) (0, 0, 0, 0) sa0 + 4h sa0 + ch da0 + ch (1, 1, 1, 1) (0, 0, 0, 0) (0, 0, 0, 0) (1, 1, 1, 1) (0, 0, 0, 0) (0, 0, 0, 0) (1, 1, 1, 1) (0, 0, 0, 0) (0, 0, 0, 0) d1 d2 d3 d1 d3 (0, 0, 0, 0) (0, 0, 0, 0) (1, 1, 1, 1) (1, 1, 1, 1) (0, 0, 0, 0) ready wait ready d0 wait ready d0 (0, 0, 0, 1) (0, 0, 0, 0) (0, 0, 0, 1) (0, 0, 0, 0) (0, 0, 0, 0) sa0 da0 sa0 + 8h (1, 1, 0) (1, 1, 0) (0, 0, 0, 0) (0, 0, 0, 0) (0, 0, 0) (0, 0, 0) d1 sa0 + 4h da0 + 4h sa0 + ch da0 + 8h da0 + ch (1, 1, 0) (0, 0, 0, 0) (0, 0, 0) (1, 1, 0) (0, 0, 0, 0) (0, 0, 0) (1, 1, 0) (0, 0, 0, 0) (0, 0, 0) (1, 1, 0) (0, 0, 0, 0) (0, 0, 0) (1, 1, 0) (0, 0, 0, 0) (0, 0, 0) (1, 1, 0) (0, 0, 0, 0) (0, 0, 0) wait ready wait ready wait ready wait ready wait ready wait d2 d3 d1 d2 d3 (0, 0, 0, 1) (0, 0, 0, 0) (0, 0, 0, 1) (0, 0, 0, 0) (0, 0, 0, 1) (0, 0, 0, 0) (0, 0, 0, 1) (0, 0, 0, 0) (0, 0, 0, 1) (0, 0, 0, 0) (0, 0, 0, 1) (0, 0, 0, 0) (0, 0, 0, 1) (0, 0, 0, 0) t1 t2 t1 t2 vbclk (input) busclk (output) vsa25 to vsa0 (input) vsbenz3 to vsbenz0 (input) vsctyp2 to vsctyp0 (input) vsstz (input) transfer response vbdi31 to vbdi0 (output) a25 to a0 (output) csz7 to csz0 (output) rdzf (output) wrz3 to wrz0 (output) bcystz (output) benz3 to benz0 (output) dc3r to dc0r (output) di31 to di0 (input) do31 to do0 (output) cpu core ? NA85E535 NA85E535 ? sram vdcsz7 to vdcsz0 (input) rdzr (output) vbdo31 to vbdo0 (input) dmactvm3 to dmactvm0 (output) dc3f to dc0f (output) dmactv3 to dmactv0 (input) dmtco3 to dmtco0 (input) dma pins vsseq2 to vsseq0 (input) t1 t2 t1 t2 dmtcom3 to dmtcom0 (output) t1 t2 t1 t2 t1 t2 da0 t1 t2 (1, 1, 1, 1) (1, 1, 1, 1) vswrite (input) (1, 1, 1, 1) (1, 1, 1, 1)
chapter 4 memory acc ess timing examples preliminary user?s manual a15555ej2v0um 159 figure 4-14. example of dma transfer timing (2-cycle transfer (using dmac with on-chip cpu core): sram sram) (5/5) (e) line transfer/without speculative read/local bus size: 32 bits cpu core ? NA85E535 NA85E535 ? sram dma pins (1, 1, 1, 1) (1, 1, 1, 1) (1, 1, 1, 1) (0, 0, 0, 0) d0 (1, 1, 1, 1) (0, 0, 0, 0) (0, 0, 0, 0) d0 (0, 0, 0, 0) sa0 sa0 + 4h da0 + 8h sa0 + ch (1, 1, 1, 1) (1, 1, 1, 1) (0, 0, 0, 0) d2 (0, 0, 0, 0) (0, 0, 0, 1) (0, 0, 0, 0) da0 da0 + 4h da0 + ch (1, 1, 1, 1) (0, 0, 0, 0) (0, 0, 0, 0) (1, 1, 1, 1) (0, 0, 0, 0) (0, 0, 0, 0) (0, 0, 0, 0) (0, 0, 0, 0) d1 d2 d3 d1 d3 (0, 0, 0, 0) (0, 0, 0, 0) (0, 0, 0, 0) ready wai t ready d0 wai t ready d0 (0, 0, 0, 1) (0, 0, 0, 0) (0, 0, 0, 1) (0, 0, 0, 0) (0, 0, 0, 0) sa0 da0 sa0 + 8h (1, 1, 0) (1, 1, 0) (0, 0, 0, 0) (0, 0, 0, 0) (0, 0, 0) (0, 0, 0) d1 sa0 + 4h da0 + 4h sa0 + ch da0 + 8h da0 + ch (1, 1, 0) (0, 0, 0, 0) (0, 0, 0) (1, 1, 0) (0, 0, 0, 0) (0, 0, 0) (1, 1, 0) (0, 0, 0, 0) (0, 0, 0) (1, 1, 0) (0, 0, 0, 0) (0, 0, 0) (1, 1, 0) (0, 0, 0, 0) (0, 0, 0) (1, 1, 0) (0, 0, 0, 0) (0, 0, 0) wai t ready wai t ready wai t ready wai t ready wai t ready wai t d2 d3 d1 d2 d3 (0, 0, 0, 1) (0, 0, 0, 0) (0, 0, 0, 1) (0, 0, 0, 0) (0, 0, 0, 1) (0, 0, 0, 0) (0, 0, 0, 1) (0, 0, 0, 0) (0, 0, 0, 1) (0, 0, 0, 0) (0, 0, 0, 1) (0, 0, 0, 0) (0, 0, 0, 1) (0, 0, 0, 0) t1 t2 t1 t2 vbclk (input) busclk (output) vsa25 to vsa0 (input) vsbenz3 to vsbenz0 (input) vsctyp2 to vsctyp0 (input) vsstz (input) transfer response vbdi31 to vbdi0 (output) a25 to a0 (output) csz7 to csz0 (output) rdzf (output) wrz3 to wrz0 (output) bcystz (output) benz3 to benz0 (output) dc3r to dc0r (output) di31 to di0 (input) do31 to do0 (output) vdcsz7 to vdcsz0 (input) rdzr (output) vbdo31 to vbdo0 (input) dmactvm3 to dmactvm0 (output) dc3f to dc0f (output) dmactv3 to dmactv0 (input) dmtco3 to dmtco0 (input) vsseq2 to vsseq0 (input) t1 t2 t1 t2 dmtcom3 to dmtcom0 (output) t1 t2 t1 t2 t1 t2 sa0 + 8h t1 t2 (0, 0, 0, 0) (1, 1, 1, 1) (1, 1, 1, 1) (1, 1, 1, 1) (0, 0, 0, 0) (1, 1, 1, 1) (1, 1, 1, 1) (1, 1, 1, 1) (0, 0, 0, 0) (1, 1, 1, 1) (0, 0, 0, 0) (1, 1, 1, 1) (1, 1, 1, 1) (1, 1, 1, 1) (0, 0, 0, 0) (1, 1, 1, 1) (0, 0, 0, 0) (1, 1, 1, 1) (0, 0, 0, 0) (1, 1, 1, 1) (0, 0, 0, 0) vswrite (input) (1, 1, 1, 1) (1, 1, 1, 1)
chapter 4 memory acc ess timing examples preliminary user?s manual a15555ej2v0um 160 figure 4-15. example of dma transfer timing (2-cycle transfer (using dmac with on-chip cpu core): sdram sdram) (1/5) (a) single transfer/without wait/cl = 2/without speculative read/local bus size: 32 bits sa0 (0, 0, 0, 1) (0, 0, 0, 0) (0, 0, 0, 0) (0, 0, 0, 0) d0 (1, 1, 1, 1) (1, 1, 1, 1) (0, 0, 0, 0) (0, 0, 0, 0) (0, 0, 0, 0) d0 col (sa0) col (da0) (1, 1, 1, 1) (0, 0, 0, 0) (1, 1, 1, 1) (0, 0, 0, 0) (1, 1, 1, 1) col (sa0) col (da0) (1, 1, 1, 1) (0, 0, 0, 0) (1, 1, 1, 1) (0, 0, 0, 0) (1, 1, 1, 1) (0, 0, 0, 0) (1, 1, 1, 1) (1, 1, 1, 1) (0, 0, 0, 0) d0 (1, 1, 0) (1, 1, 0) (0, 0, 0, 0) (0, 0, 0, 0) (0, 0, 0) (0, 0, 0) wait wait ready ready d0 da0 d0 (0, 0, 0, 1) (0, 0, 0, 0) (0, 0, 0, 1) (0, 0, 0, 0) (0, 0, 0, 1) (0, 0, 0, 0) wait ready d0 wait ready d0 (0, 0, 0, 1) (0, 0, 0, 0) (0, 0, 0, 1) (0, 0, 0, 0) (0, 0, 0, 0) (1, 1, 0) (1, 1, 0) (0, 0, 0, 0) (0, 0, 0, 0) (0, 0, 0) (0, 0, 0) sa0 da0 tread tlate t0 twr vbclk (input) busclk (output) vsa25 to vsa0 (input) vsbenz3 to vsbenz0 (input) vsctyp2 to vsctyp0 (input) vsstz (input) transfer response vbdi31 to vbdi0 (output) a25 to a0 (output) csz7 to csz0 (output) sdrasz (output) sdwez (output) bcystz (output) benz3 to benz0 (output) dc3r to dc0r (output) di31 to di0 (input) do31 to do0 (output) cpu core ? NA85E535 NA85E535 ? sdram vdcsz7 to vdcsz0 (input) sdcasz (output) vbdo31 to vbdo0 (input) dmactvm3 to dmactvm0 (output) dc3f to dc0f (output) dmactv3 to dmactv0 (input) dmtco3 to dmtco0 (input) dma pins vsseq2 to vsseq0 (input) dmtcom3 to dmtcom0 (output) dqm3 to dqm0 (output) t0 tlate tread tlate t0 twr t0 tlate h (1, 1, 1, 1) (0, 0, 0, 0) (1, 1, 1, 1) (0, 0, 0, 0) (1, 1, 1, 1) (0, 0, 0, 0) (1, 1, 1, 1) (0, 0, 0, 0) (1, 1, 1, 1) d0 vswrite (input)
chapter 4 memory acc ess timing examples preliminary user?s manual a15555ej2v0um 161 figure 4-15. example of dma transfer timing (2-cycle transfer (using dmac with on-chip cpu core): sdram sdram) (2/5) (b) block transfer/with speculative read/local bus size: 32 bits speculative read cycle (0, 0, 0, 0) (1, 1, 1, 1) (0, 0, 0, 0) (0, 0, 0, 0) d0 (1, 1, 1, 1) (0, 0, 0, 0) (0, 0, 0, 0) col (sa0) (1, 1, 1, 1) (1, 1, 1, 1) (0, 0, 0, 0) (1, 1, 1, 1) (0, 0, 0, 0) d2 (0, 0, 0, 0) (0, 0, 0, 1) (0, 0, 0, 0) (0, 0, 0, 0) (0, 0, 0, 0) (1, 1, 1, 1) (1, 1, 1, 1) (0, 0, 0, 0) (1, 1, 1, 1) (0, 0, 0, 0) (1, 1, 1, 1) (0, 0, 0, 0) d1 d3 ready da0 + ch (1, 1, 0) (0, 0, 0, 0) (0, 0, 0) wait d3 (0, 0, 0, 1) (0, 0, 0, 0) (0, 0, 0, 1) (0, 0, 0, 0) sa0 + 8h sa0 + ch da0 + 8h (1, 1, 0) (0, 0, 0, 0) (0, 0, 0) (1, 1, 0) (0, 0, 0, 0) (0, 0, 0) (1, 1, 0) (0, 0, 0, 0) (0, 0, 0) ready wait ready wait ready wait ready d2 d3 d1 d2 (0, 0, 0, 0) (0, 0, 0, 1) (0, 0, 0, 0) (0, 0, 0, 1) (0, 0, 0, 0) (0, 0, 0, 1) (0, 0, 0, 0) wait ready d0 wait ready d0 (0, 0, 0, 1) (0, 0, 0, 0) (0, 0, 0, 1) (0, 0, 0, 0) (0, 0, 0, 0) sa0 da0 (1, 1, 0) (1, 1, 0) (0, 0, 0, 0) (0, 0, 0, 0) (0, 0, 0) (0, 0, 0) d1 sa0 + 4h da0 + 4h (1, 1, 0) (0, 0, 0, 0) (0, 0, 0) (1, 1, 0) (0, 0, 0, 0) (0, 0, 0) wait ready wait (0, 0, 0, 1) (0, 0, 0, 0) (0, 0, 0, 1) tread tread tlate tw vbclk (input) busclk (output) vsa25 to vsa0 (input) vsbenz3 to vsbenz0 (input) vsctyp2 to vsctyp0 (input) vsstz (input) transfer response vbdi31 to vbdi0 (output) a25 to a0 (output) csz7 to csz0 (output) sdrasz (output) dqm3 to dqm0 (output) bcystz (output) benz3 to benz0 (output) dc3r to dc0r (output) di31 to di0 (input) do31 to do0 (output) cpu core ? NA85E535 NA85E535 ? sdram vdcsz7 to vdcsz0 (input) sdcasz (output) vbdo31 to vbdo0 (input) dmactvm3 to dmactvm0 (output) dc3f to dc0f (output) dmactv3 to dmactv0 (input) dmtco3 to dmtco0 (input) dma pin vsseq2 to vsseq0 (input) t0 dmtcom3 to dmtcom0 (output) tread tlate twr twr sdwez (output) t0 tread t0 twr t0 twr col (da0) h (1, 1, 1, 1) (1, 1, 1, 1) (0, 0, 0, 0) (1, 1, 1, 1) (0, 0, 0, 0) (1, 1, 1, 1) (1, 1, 1, 1) (1, 1, 1, 1) (0, 0, 0, 0) (0, 0, 0, 0) (1, 1, 1, 1) (1, 1, 1, 1) d1 d0 d2 d3 vswrite (input) col (sa0 + 4h) col (sa0 + 8h) col (sa0 + ch) col (da0 + 4h) col (da0 + 8h) col (da0 + ch)
chapter 4 memory acc ess timing examples preliminary user?s manual a15555ej2v0um 162 figure 4-15. example of dma transfer timing (2-cycle transfer (using dmac with on-chip cpu core): sdram sdram) (3/5) (c) block transfer/without speculative read/local bus size: 32 bits (0, 0, 0, 0) (1, 1, 1, 1) (1, 1, 1, 1) (1, 1, 1, 1) (0, 0, 0, 0) d0 (1, 1, 1, 1) (0, 0, 0, 0) (0, 0, 0, 0) d0 (0, 0, 0, 0) col (sa0) (1, 1, 1, 1) (0, 0, 0, 0) d2 (0, 0, 0, 0) (0, 0, 0, 1) (0, 0, 0, 0) col (da0) (1, 1, 1, 1) (0, 0, 0, 0) (0, 0, 0, 0) (0, 0, 0, 0) (0, 0, 0, 0) (0, 0, 0, 0) (0, 0, 0, 0) d1 d2 d3 d1 d3 (0, 0, 0, 0) (0, 0, 0, 0) (1, 1, 1, 1) (1, 1, 1, 1) (0, 0, 0, 0) (0, 0, 0, 0) (0, 0, 0, 0) (1, 1, 1, 1) (0, 0, 0, 0) (1, 1, 1, 1) (0, 0, 0, 0) (1, 1, 1, 1) (1, 1, 1, 1) (0, 0, 0, 0) ready wait ready d0 wait ready d0 (0, 0, 0, 1) (0, 0, 0, 0) (0, 0, 0, 1) (0, 0, 0, 0) (0, 0, 0, 0) sa0 da0 sa0 + 8h (1, 1, 0) (1, 1, 0) (0, 0, 0, 0) (0, 0, 0, 0) (0, 0, 0) (0, 0, 0) d1 sa0 + 4h da0 + 4h sa0 + ch da0 + 8h da0 + ch (1, 1, 0) (0, 0, 0, 0) (0, 0, 0) (1, 1, 0) (0, 0, 0, 0) (0, 0, 0) (1, 1, 0) (0, 0, 0, 0) (0, 0, 0) (1, 1, 0) (0, 0, 0, 0) (0, 0, 0) (1, 1, 0) (0, 0, 0, 0) (0, 0, 0) (1, 1, 0) (0, 0, 0, 0) (0, 0, 0) wait ready wait ready wait ready wait ready wait ready wait d2 d3 d1 d2 d3 (0, 0, 0, 1) (0, 0, 0, 0) (0, 0, 0, 1) (0, 0, 0, 0) (0, 0, 0, 1) (0, 0, 0, 0) (0, 0, 0, 1) (0, 0, 0, 0) (0, 0, 0, 1) (0, 0, 0, 0) (0, 0, 0, 1) (0, 0, 0, 0) (0, 0, 0, 1) (0, 0, 0, 0) vbclk (input) busclk (output) vsa25 to vsa0 (input) vsbenz3 to vsbenz0 (input) vsctyp2 to vsctyp0 (input) vsstz (input) transfer response vbdi31 to vbdi0 (output) a25 to a0 (output) csz7 to csz0 (output) sdrasz (output) dqm3 to dqm0 (output) bcystz (output) benz3 to benz0 (output) dc3r to dc0r (output) di31 to di0 (input) do31 to do0 (output) cpu core ? NA85E535 NA85E535 ? sdram vdcsz7 to vdcsz0 (input) sdcasz (output) vbdo31 to vbdo0 (input) dmactvm3 to dmactvm0 (output) dc3f to dc0f (output) dmactv3 to dmactv0 (input) dmtco3 to dmtco0 (input) dma pins vsseq2 to vsseq0 (input) dmtcom3 to dmtcom0 (output) sdwez (output) tread tlate twr tlate t0 t0 tread tlate twr tlate t0 t0 tread tlate twr tlate t0 t0 tread tlate twr tlate t0 t0 h (0, 0, 0, 0) (1, 1, 1, 1) (1, 1, 1, 1) (0, 0, 0, 0) (1, 1, 1, 1) (1, 1, 1, 1) (1, 1, 1, 1) (1, 1, 1, 1) (0, 0, 0, 0) (1, 1, 1, 1) (0, 0, 0, 0) (1, 1, 1, 1) (1, 1, 1, 1) (1, 1, 1, 1) (1, 1, 1, 1) (0, 0, 0, 0) (1, 1, 1, 1) (0, 0, 0, 0) (1, 1, 1, 1) (1, 1, 1, 1) (1, 1, 1, 1) vswrite (input) col (sa0 + 4h) col (sa0 + 8h) col (sa0 + ch) col (da0 + 4h) col (da0 + 8h) col (da0 + ch)
chapter 4 memory acc ess timing examples preliminary user?s manual a15555ej2v0um 163 figure 4-15. example of dma transfer timing (2-cycle transfer (using dmac with on-chip cpu core): sdram sdram) (4/5) (d) line transfer/with speculative read/local bus size: 32 bits (1, 1, 1, 1) (1, 1, 1, 1) (1, 1, 1, 1) (0, 0, 0, 0) (1, 1, 1, 1) (0, 0, 0, 0) (0, 0, 0, 0) d0 (0, 0, 0, 0) col (sa0) (1, 1, 1, 1) (0, 0, 0, 0) d2 (0, 0, 0, 0) (0, 0, 0, 1) (0, 0, 0, 0) col ( da0) (0, 0, 0, 0) (0, 0, 0, 0) (0, 0, 0, 0) (0, 0, 0, 0) (0, 0, 0, 0) (0, 0, 0, 0) d1 d3 (0, 0, 0, 0) (0, 0, 0, 0) (1, 1, 1, 1) (0, 0, 0, 0) (0, 0, 0, 0) ready wai t ready d0 wai t ready d0 (0, 0, 0, 1) (0, 0, 0, 0) (0, 0, 0, 1) (0, 0, 0, 0) (0, 0, 0, 0) sa0 da0 sa0 + 8h (1, 1, 0) (1, 1, 0) (0, 0, 0, 0) (0, 0, 0, 0) (0, 0, 0) (0, 0, 0) d1 sa0 + 4h da0 + 4h sa0 + ch da0 + 8h da0 + ch (1, 1, 0) (0, 0, 0, 0) (0, 0, 0) (1, 1, 0) (0, 0, 0, 0) (0, 0, 0) (1, 1, 0) (0, 0, 0, 0) (0, 0, 0) (1, 1, 0) (0, 0, 0, 0) (0, 0, 0) (1, 1, 0) (0, 0, 0, 0) (0, 0, 0) (1, 1, 0) (0, 0, 0, 0) (0, 0, 0) wai t ready wai t ready wai t ready wai t ready wai t ready wai t d2 d3 d1 d2 d3 (0, 0, 0, 1) (0, 0, 0, 0) (0, 0, 0, 1) (0, 0, 0, 0) (0, 0, 0, 1) (0, 0, 0, 0) (0, 0, 0, 1) (0, 0, 0, 0) (0, 0, 0, 1) (0, 0, 0, 0) (0, 0, 0, 1) (0, 0, 0, 0) (0, 0, 0, 1) (0, 0, 0, 0) vbclk (input) busclk (output) vsa25 to vsa0 (input) vsbenz3 to vsbenz0 (input) vsctyp2 to vsctyp0 (input) vsstz (input) transfer response vbdi31 to vbdi0 (output) a25 to a0 (output) csz7 to csz0 (output) sdrasz (output) dqm3 to dqm0 (output) bcystz (output) benz3 to benz0 (output) dc3r to dc0r (output) di31 to di0 (input) do31 to do0 (output) cpu core ? NA85E535 NA85E535 ? sdram vdcsz7 to vdcsz0 (input) sdcasz (output) vbdo31 to vbdo0 (input) dmactvm3 to dmactvm0 (output) dc3f to dc0f (output) dmactv3 to dmactv0 (input) dmtco3 to dmtco0 (input) dma pins vsseq2 to vsseq0 (input) dmtcom3 to dmtcom0 (output) sdwez (output) tread tread tlate tread t0 tlate twr twr tw t0 twr t0 twr t0 h (0, 0, 0, 0) (1, 1, 1, 1) (1, 1, 1, 1) (1, 1, 1, 1) (1, 1, 1, 1) (1, 1, 1, 1) tread (1, 1, 1, 1) (1, 1, 1, 1) (1, 1, 1, 1) (1, 1, 1, 1) (1, 1, 1, 1) (1, 1, 1, 1) d0 d1 d2 d3 vswrite (input) col (sa0 + 4h) col (sa0 + 8h) col (sa0 + ch) col (da0 + 4h) col (da0 + 8h) col (da0 + ch) speculative read cycle
chapter 4 memory acc ess timing examples preliminary user?s manual a15555ej2v0um 164 figure 4-15. example of dma transfer timing (2-cycle transfer (using dmac with on-chip cpu core): sdram sdram) (5/5) (e) line transfer/without speculative read/local bus size: 32 bits (1, 1, 1, 1) (1, 1, 1, 1) (1, 1, 1, 1) (0, 0, 0, 0) (1, 1, 1, 1) (0, 0, 0, 0) (0, 0, 0, 0) d0 (0, 0, 0, 0) col ( sa0) (1, 1, 1, 1) (0, 0, 0, 0) d2 (0, 0, 0, 0) (0, 0, 0, 1) (0, 0, 0, 0) col ( da0) (0, 0, 0, 0) (0, 0, 0, 0) (0, 0, 0, 0) (0, 0, 0, 0) (0, 0, 0, 0) (0, 0, 0, 0) d1 d3 (0, 0, 0, 0) (0, 0, 0, 0) (1, 1, 1, 1) (0, 0, 0, 0) ready wait ready d0 wait ready d0 (0, 0, 0, 1) (0, 0, 0, 0) (0, 0, 0, 1) (0, 0, 0, 0) (0, 0, 0, 0) sa0 da0 sa0 + 8h (1, 1, 0) (1, 1, 0) (0, 0, 0, 0) (0, 0, 0, 0) (0, 0, 0) (0, 0, 0) d1 sa0 + 4h da0 + 4h sa0 + ch da0 + 8h da0 + ch (1, 1, 0) (0, 0, 0, 0) (0, 0, 0) (1, 1, 0) (0, 0, 0, 0) (0, 0, 0) (1, 1, 0) (0, 0, 0, 0) (0, 0, 0) (1, 1, 0) (0, 0, 0, 0) (0, 0, 0) (1, 1, 0) (0, 0, 0, 0) (0, 0, 0) (1, 1, 0) (0, 0, 0, 0) (0, 0, 0) wait ready wait ready wait ready wait ready wait ready wait d2 d3 d1 d2 d3 (0, 0, 0, 1) (0, 0, 0, 0) (0, 0, 0, 1) (0, 0, 0, 0) (0, 0, 0, 1) (0, 0, 0, 0) (0, 0, 0, 1) (0, 0, 0, 0) (0, 0, 0, 1) (0, 0, 0, 0) (0, 0, 0, 1) (0, 0, 0, 0) (0, 0, 0, 1) (0, 0, 0, 0) vbclk (input) busclk (output) vsa25 to vsa0 (input) vsbenz3 to vsbenz0 (input) vsctyp2 to vsctyp0 (input) vsstz (input) transfer response vbdi31 to vbdi0 (output) a25 to a0 (output) csz7 to csz0 (output) sdrasz (output) dqm3 to dqm0 (output) bcystz (output) benz3 to benz0 (output) dc3r to dc0r (output) di31 to di0 (input) do31 to do0 (output) cpu core ? NA85E535 NA85E535 ? sdram vdcsz7 to vdcsz0 (input) sdcasz (output) vbdo31 to vbdo0 (input) dmactvm3 to dmactvm0 (output) dc3f to dc0f (output) dmactv3 to dmactv0 (input) dmtco3 to dmtco0 (input) dma pins vsseq2 to vsseq0 (input) dmtcom3 to dmtcom0 (output) sdwez (output) tread tlate t0 tlate h (0, 0, 0, 0) (1, 1, 1, 1) (1, 1, 1, 1) (1, 1, 1, 1) (1, 1, 1, 1) (1, 1, 1, 1) (1, 1, 1, 1) (1, 1, 1, 1) (1, 1, 1, 1) (1, 1, 1, 1) (1, 1, 1, 1) (1, 1, 1, 1) twr t0 tread tlate t0 tlate twr t0 tread tlate t0 tlate twr t0 tread tlate t0 tlate twr t0 (1, 1, 1, 1) (0, 0, 0, 0) (0, 0, 0, 0) (0, 0, 0, 0) (0, 0, 0, 0) (1, 1, 1, 1) (1, 1, 1, 1) (0, 0, 0, 0) (0, 0, 0, 0) (1, 1, 1, 1) (1, 1, 1, 1) (0, 0, 0, 0) (0, 0, 0, 0) (1, 1, 1, 1) (1, 1, 1, 1) (1, 1, 1, 1) (0, 0, 0, 0) (1, 1, 1, 1) (0, 0, 0, 0) (1, 1, 1, 1) (0, 0, 0, 0) d0 d1 d2 d3 vswrite (input) col (sa0 + ch) col (da0 + 4h) col (da0 + 8h) col (da0 + ch) col (sa0 + 4h) col (sa0 + 8h)
chapter 4 memory acc ess timing examples preliminary user?s manual a15555ej2v0um 165 figure 4-16. example of dma transfer timing (2-cycle transfer (using dmac with on-chip cpu core): sram npb (single transfer/with speculative read/local bus size: 32 bits)) (1, 1, 1, 1) d0 (0, 0, 0, 0) sa0 sa0 + 8h (0, 0, 0, 0) (0, 0, 0, 1) (0, 0, 0, 0) sa0 + 4h sa0 + ch d1 d2 d3 da0 + ch d3 ? 1 (0, 0, 0, 0) (0, 0, 0, 1) (0, 0, 0, 0) sa0 + 8h sa0 + ch da0 + 8h (1, 1, 0) (0, 0, 0, 0) (0, 0, 0) (1, 1, 0) (0, 0, 0, 0) (0, 0, 0) wait wait d2 d3 d1 ? 1 d2 ? 1 (0, 0, 0, 0) (0, 0, 0, 1) (0, 0, 0, 0) (0, 0, 0, 0) (0, 0, 0, 1) (0, 0, 0, 0) d0 ? 1 wait ready d0 (0, 0, 0, 1) (0, 0, 0, 0) (0, 0, 0, 0) sa0 da0 (1, 1, 0) (1, 1, 0) (0, 0, 0, 0) (1, 1, 0, 0) (0, 0, 0) (0, 0, 1) d1 sa0 + 4h da0 + 4h (1, 1, 0) (0, 0, 0, 0) (0, 0, 0) wait (0, 0, 0, 1) (0, 0, 0, 0) (1, 1, 1, 1) t1 t2 t1 t2 vbclk (input) busclk (output) vsa25 to vsa0 (input) vsbenz3 to vsbenz0 (input) vsctyp2 to vsctyp0 (input) vsstz (input) transfer response not e (output) vbdi31 to vbdi0 (output) a25 to a0 (output) csz7 to csz0 (output) rdzf (output) wrz3 to wrz0 (output) bcystz (output) benz3 to benz0 (output) dc3r to dc0r (output) di31 to di0 (input) cpu core ? NA85E535 NA85E535 ? sram vdcsz7 to vdcsz0 (input) rdzr (output) vbdo31 to vbdo0 (input) dmactvm3 to dmactvm0 (output) dc3f to dc0f (output) dmactv3 to dmactv0 (input) dmtco3 to dmtco0 (input) dma pins (0, 0, 0, 1) (0, 0, 0, 0) vsseq2 to vsseq0 (input) (0, 0, 0, 0) (0, 0, 0, 0) dmtcom3 to dmtcom0 (output) (0, 0, 0, 0) ready ready ready (0, 0, 0, 1) (0, 0, 0, 1) (0, 0, 0, 1) t1 t2 t1 t2 (1, 1, 1, 1) (1, 1, 1, 1) npb npb npb npb vswrite (input) da0 + 2h da0 + 6h da0 + ah da0 + eh (1, 1, 0) (1, 1, 0, 0) (0, 0, 0) (1, 1, 0) (1, 1, 0, 0) (1, 0, 0) (1, 1, 0) (1, 1, 0, 0) (0, 0, 0) (1, 1, 0) (1, 1, 0, 0) (0, 0, 1) (1, 1, 0) (1, 1, 0, 0) (0, 0, 0) (1, 1, 0) (1, 1, 0, 0) (1, 0, 0) (1, 1, 0) (1, 1, 0, 0) (0, 0, 0) d0 ? 2 d1 ? 2 d2 ? 2 d3 ? 2 speculative read cycle note transfer response output by NA85E535
chapter 4 memory acc ess timing examples preliminary user?s manual a15555ej2v0um 166 figure 4-17. example of dma transfer timing (2-cycle transfer (using dmac with on-chip cpu core): npb sram (single transfer/local bus size: 32 bits)) d0 da0 da0 + 8h (0, 0, 0, 1) (0, 0, 0, 0) da0 + 4h da0 + ch d1 d2 d3 da0 + ch (1, 1, 0) (0, 0, 0, 0) (0, 0, 0) (0, 0, 0, 1) (0, 0, 0, 0) (0, 0, 0, 1) (0, 0, 0, 0) sa0 + 8h sa0 + ch da0 + 8h (1, 1, 0) (0, 0, 0, 0) (0, 0, 0) wait (0, 0, 0, 0) (0, 0, 0, 0) (0, 0, 0, 1) (0, 0, 0, 0) (0, 0, 0, 0) d0 wait (0, 0, 0, 0) (0, 0, 0, 1) (0, 0, 0, 0) sa0 da0 (1, 1, 0) (1, 1, 0) (1, 1, 0, 0) (0, 0, 0, 0) (1, 0, 0) (0, 0, 0) sa0 + 4h da0 + 4h (1, 1, 0) (0, 0, 0, 0) (0, 0, 0) wait (0, 0, 0, 0) (0, 0, 0, 1) t1 t2 t1 t2 vbclk (input) busclk (output) vsa25 to vsa0 (input) vsbenz3 to vsbenz0 (input) vsctyp2 to vsctyp0 (input) vsstz (input) transfer response not e (output) a25 to a0 (output) csz7 to csz0 (output) rdzf (output) wrz3 to wrz0 (output) bcystz (output) benz3 to benz0 (output) dc3r to dc0r (output) do31 to do0 (output) cpu core ? NA85E535 NA85E535 ? sram vdcsz7 to vdcsz0 (input) rdzr (output) vbdo31 to vbdo0 (input) dmactvm3 to dmactvm0 (output) ready dc3f to dc0f (output) ready dmactv3 to dmactv0 (input) dmtco3 to dmtco0 (input) dma pins (0, 0, 0, 1) (0, 0, 0, 0) vsseq2 to vsseq0 (input) (0, 0, 0, 0) (0, 0, 0, 0) dmtcom3 to dmtcom0 (output) (0, 0, 0, 0) ready ready (0, 0, 0, 1) (0, 0, 0, 1) (0, 0, 0, 1) t1 t2 t1 t2 npb npb npb npb wait ready h h (0, 0, 0, 0) (0, 0, 0, 0) (0, 0, 0, 0) (0, 0, 0, 0) (1, 1, 1, 1) (0, 0, 0, 0) (0, 0, 0, 0) (0, 0, 0, 0) (0, 0, 0, 0) (1, 1, 1, 1) (1, 1, 1, 1) (1, 1, 1, 1) (1, 1, 1, 1) (0, 0, 0, 0) (1, 1, 1, 1) (1, 1, 1, 1) (1, 1, 1, 1) (0, 0, 0, 0) (1, 1, 1, 1) (1, 1, 1, 1) (1, 1, 1, 1) (0, 0, 0, 0) (1, 1, 1, 1) (1, 1, 1, 1) (1, 1, 1, 1) (0, 0, 0, 0) (1, 1, 1, 1) vswrite (input) sa0 + 2h sa0 + 6h sa0 + ah sa0 + eh (1, 1, 0) (1, 1, 0, 0) (0, 0, 0) (1, 1, 0) (1, 1, 0, 0) (1, 0, 0) (1, 1, 0) (1, 1, 0, 0) (0, 0, 0) (1, 1, 0) (1, 1, 0, 0) (1, 0, 0) (1, 1, 0) (1, 1, 0, 0) (0, 0, 0) (1, 1, 0) (1, 1, 0, 0) (1, 0, 0) (1, 1, 0) (1, 1, 0, 0) (0, 0, 0) d1 d2 d3 note transfer response output by NA85E535
chapter 4 memory acc ess timing examples preliminary user?s manual a15555ej2v0um 167 figure 4-18. example of dma transfer timing (2-cycle transfer (using dmac with on-chip cpu core): npb npb (single transfer/during speculative read/local bus size: 32 bits)) (0, 0, 0, 0) d0 a0 (0, 0, 0, 0) da0 (1, 1, 0) (1, 1, 0, 0) (0, 0, 0) (0, 0, 0, 0) (0, 0, 0, 1) d0 wait ready (0, 0, 0, 0) (0, 0, 0, 1) (0, 0, 0, 0) (0, 0, 0, 0) a0 sa0 (0, 0, 1) (1, 1, 0) (0, 0, 0, 0) (1, 1, 0, 0) (0, 0, 0) (0, 0, 0) da0 sa0 (1, 1, 0) (1, 1, 0, 0) (0, 0, 0) (1, 1, 0) (1, 1, 0, 0) (0, 0, 0) (0, 0, 0, 1) (0, 0, 0, 0) (0, 0, 0, 1) t1 t2 vbclk (input) busclk (output) vsa25 to vsa0 (input) vsbenz3 to vsbenz0 (input) vsctyp2 to vsctyp0 (input) vsstz (input) transfer response note (output) a25 to a0 (output) csz7 to csz0 (output) rdzf (output) wrz3 to wrz0 (output) bcystz (output) benz3 to benz0 (output) dc3r to dc0r (output) di31 to di0 (input) cpu core ? NA85E535 NA85E535 ? sram vdcsz7 to vdcsz0 (input) rdzr (output) vbdi31 to vbdi0 (output) dmactvm3 to dmactvm0 (output) dc3f to dc0f (output) dmactv3 to dmactv0 (input) dmtco3 to dmtco0 (input) dma pins vsseq2 to vsseq0 (input) dmtcom3 to dmtcom0 (output) npb npb npb npb (1, 1, 1, 1) (0, 0, 0, 0) (1, 1, 1, 1) (1, 1, 1, 1) (0, 0, 0, 0) (0, 0, 0, 1) (0, 0, 0, 0) a0 + 4h t1 t2 a0 + 8h t1 t2 a0 + ch t1 t2 (0, 0, 0, 0) (1, 1, 1, 1) (0, 0, 0, 0) d1 d2 d3 (0, 0, 0, 1) (0, 0, 0, 0) vswrite (input) note transfer response output by NA85E535 remark the 2-cycle transfer of npb npb is executed regardless of an external memory access by the NA85E535.
chapter 4 memory acc ess timing examples preliminary user?s manual a15555ej2v0um 168 figure 4-19. example of dma transfer timing (2-cycle transfer (using dmac with on-chip cpu core): npb ram (single transfer/during speculative read/local bus size: 32 bits)) (0, 0, 0, 0) d0 a0 (0, 0, 0, 0) d0 wait ready (0, 0, 0, 0) (0, 0, 0, 1) (0, 0, 0, 0) (0, 0, 0, 0) a0 sa0 (0, 0, 1) (1, 1, 0) (0, 0, 0, 0) (1, 1, 0, 0) (0, 0, 0) (0, 0, 0) t1 t2 vbclk (input) busclk (output) vsa25 to vsa0 (input) vsbenz3 to vsbenz0 (input) vsctyp2 to vsctyp0 (input) vsstz (input) transfer response note (output) a25 to a0 (output) csz7 to csz0 (output) rdzf (output) wrz3 to wrz0 (output) bcystz (output) benz3 to benz0 (output) dc3r to dc0r (output) di31 to di0 (input) cpu core ? NA85E535 NA85E535 ? sram vdcsz7 to vdcsz0 (input) rdzr (output) vbdi31 to vbdi0 (output) dmactvm3 to dmactvm0 (output) dc3f to dc0f (output) dmactv3 to dmactv0 (input) dmtco3 to dmtco0 (input) dma pins vsseq2 to vsseq0 (input) dmtcom3 to dmtcom0 (output) npb ram (1, 1, 1, 1) (0, 0, 0, 0) (1, 1, 1, 1) (1, 1, 1, 1) a0 + 4h t1 t2 a0 + 8h t1 t2 a0 + ch t1 t2 (0, 0, 0, 0) (1, 1, 1, 1) (0, 0, 0, 0) d1 d2 d3 vswrite (input) (0, 0, 0, 1) (0, 0, 0, 0) (0, 0, 0, 1) (0, 0, 0, 0) note transfer response output by NA85E535 remark the 2-cycle transfer of npb ram is executed regardless of an external memory access by the NA85E535.
chapter 4 memory acc ess timing examples preliminary user?s manual a15555ej2v0um 169 figure 4-20. example of dma transfer timing (2-cycle transfer (with na85e300): sram sram) (1/5) (a) single transfer/without wait/without speculative read/local bus size: 32 bits sa0 (0, 0, 0, 1) (0, 0, 0, 0) (1, 1, 1, 1) (0, 0, 0, 0) d0 (1, 1, 1, 1) (1, 1, 1, 1) (0, 0, 0, 0) (0, 0, 0, 0) (0, 0, 0, 0) d0 (0, 0, 0, 0) sa0 da0 (1, 1, 1, 1) (1, 1, 1, 1) (0, 0, 0, 0) (1, 1, 1, 1) (0, 0, 0, 0) (1, 1, 1, 1) sa0 da0 (0, 0, 0, 0) (1, 1, 1, 1) (1, 1, 1, 1) (1, 1, 1, 1) (0, 0, 0, 0) (1, 1, 1, 1) (0, 0, 0, 0) (1, 1, 1, 1) (0, 0, 0, 0) (1, 1, 1, 1) (1, 1, 1, 1) (0, 0, 0, 0) d0 d0 (1, 1, 0) (1, 1, 0) (0, 0, 0, 0) (0, 0, 0, 0) (0, 0, 0) (0, 0, 0) wait wait ready ready d0 da0 d0 (1, 1, 1, 0) (1, 1, 1, 1) (1, 1, 1, 0) (1, 1, 1, 1) (0, 0, 0, 1) (0, 0, 0, 0) wait ready d0 wait ready d0 (1, 1, 1, 0) (1, 1, 1, 1) (1, 1, 1, 0) (1, 1, 1, 1) (0, 0, 0, 0) (1, 1, 0) (1, 1, 0) (0, 0, 0, 0) (0, 0, 0, 0) (0, 0, 0) (0, 0, 0) sa0 da0 t1 t2 t1 t2 vbclk (input) busclk (output) vsa25 to vsa0 (input) vswrite (input) vsbenz3 to vsbenz0 (input) vsctyp2 to vsctyp0 (input) vsstz (input) transfer response vbdi31 to vbdi0 (output) a25 to a0 (output) csz7 to csz0 (output) rdzf (output) wrz3 to wrz0 (output) bcystz (output) benz3 to benz0 (output) dc3r to dc0r (output) di31 to di0 (input) do31 to do0 (output) cpu core ? NA85E535 NA85E535 ? sram rdzr (output) vbdo31 to vbdo0 (input) dmxczm03 to dmxczm00 (output) dc3f to dc0f (output) dmxcsz03 to dmxcsz00 (input) dmxtco03 to dmxtco00 (input) dma pins vsseq2 to vsseq0 (input) t1 t2 t1 t2 dmxtcm03 to dmxtcm00 (output) vdcsz7 to vdcsz0 (input)
chapter 4 memory acc ess timing examples preliminary user?s manual a15555ej2v0um 170 figure 4-20. example of dma transfer timing (2-cycle transfer (with na85e300): sram sram) (2/5) (b) block transfer/with speculative read/local bus size: 32 bits da0 + 4h (0, 0, 0, 0) (1, 1, 1, 1) (1, 1, 1, 1) (1, 1, 1, 1) (1, 1, 1, 1) d0 (1, 1, 1, 1) (0, 0, 0, 0) (0, 0, 0, 0) d0 (0, 0, 0, 0) sa0 sa0 + 8h da0 da0 + 8h (1, 1, 1, 1) (1, 1, 1, 1) (0, 0, 0, 0) (1, 1, 1, 1) (0, 0, 0, 0) d2 (0, 0, 0, 0) (0, 0, 0, 1) (0, 0, 0, 0) sa0 + 4h sa0 + ch da0 + ch (1, 1, 1, 1) (0, 0, 0, 0) (0, 0, 0, 0) (1, 1, 1, 1) (0, 0, 0, 0) (1, 1, 1, 1) (0, 0, 0, 0) (1, 1, 1, 1) (0, 0, 0, 0) (1, 1, 1, 1) (0, 0, 0, 0) d1 d2 d3 d1 d3 ready da0 + ch (1, 1, 0) (0, 0, 0, 0) (0, 0, 0) wait d3 (1, 1, 1, 0) (1, 1, 1, 1) (0, 0, 0, 1) (0, 0, 0, 0) sa0 + 8h sa0 + ch da0 + 8h (1, 1, 0) (0, 0, 0, 0) (0, 0, 0) (1, 1, 0) (0, 0, 0, 0) (0, 0, 0) (1, 1, 0) (0, 0, 0, 0) (0, 0, 0) ready wait ready wait ready wait ready d2 d3 d1 d2 (1, 1, 1, 1) (1, 1, 1, 0) (1, 1, 1, 1) (1, 1, 1, 0) (1, 1, 1, 1) (1, 1, 1, 0) (1, 1, 1, 1) wait ready d0 wait ready d0 (1, 1, 1, 0) (1, 1, 1, 1) (1, 1, 1, 0) (1, 1, 1, 1) (0, 0, 0, 0) sa0 da0 (1, 1, 0) (1, 1, 0) (0, 0, 0, 0) (0, 0, 0, 0) (0, 0, 0) (0, 0, 0) d1 sa0 + 4h da0 + 4h (1, 1, 0) (0, 0, 0, 0) (0, 0, 0) (1, 1, 0) (0, 0, 0, 0) (0, 0, 0) wait ready wait (1, 1, 1, 0) (1, 1, 1, 1) (1, 1, 1, 0) t1 t2 t1 t2 vbclk (input) busclk (output) vsa25 to vsa0 (input) vsbenz3 to vsbenz0 (input) vsctyp2 to vsctyp0 (input) vsstz (input) transfer response vbdi31 to vbdi0 (output) a25 to a0 (output) csz7 to csz0 (output) rdzf (output) wrz3 to wrz0 (output) bcystz (output) benz3 to benz0 (output) dc3r to dc0r (output) di31 to di0 (input) do31 to do0 (output) cpu core ? NA85E535 NA85E535 ? sram vdcsz7 to vdcsz0 (input) rdzr (output) vbdo31 to vbdo0 (input) dmxczm03 to dmxczm00 (output) dc3f to dc0f (output) dmxcsz03 to dmxcsz00 (input) dmxtco03 to dmxtco00 (input) dma pins vsseq2 to vsseq0 (input) t1 t2 t1 t2 dmxtcm03 to dmxtcm00 (output) t1 t2 t1 t2 t1 t2 t1 t2 vswrite (input) (1, 1, 1, 1) (1, 1, 1, 1)
chapter 4 memory acc ess timing examples preliminary user?s manual a15555ej2v0um 171 figure 4-20. example of dma transfer timing (2-cycle transfer (with na85e300): sram sram) (3/5) (c) block transfer/without speculative read/local bus size: 32 bits (0, 0, 0, 0) (1, 1, 1, 1) (1, 1, 1, 1) (1, 1, 1, 1) (1, 1, 1, 1) d0 (1, 1, 1, 1) (0, 0, 0, 0) (0, 0, 0, 0) d0 (0, 0, 0, 0) sa0 sa0 + 4h sa0 + 8h sa0 + ch (1, 1, 1, 1) (1, 1, 1, 1) (0, 0, 0, 0) (1, 1, 1, 1) (0, 0, 0, 0) d2 (0, 0, 0, 0) (0, 0, 0, 1) (0, 0, 0, 0) da0 da0 + 4h da0 + 8h da0 + ch (1, 1, 1, 1) (0, 0, 0, 0) (0, 0, 0, 0) (1, 1, 1, 1) (0, 0, 0, 0) (1, 1, 1, 1) (0, 0, 0, 0) (1, 1, 1, 1) (0, 0, 0, 0) (1, 1, 1, 1) (0, 0, 0, 0) d1 d2 d3 d1 d3 (0, 0, 0, 0) (0, 0, 0, 0) (0, 0, 0, 0) (1, 1, 1, 1) (1, 1, 1, 1) (0, 0, 0, 0) (0, 0, 0, 0) (0, 0, 0, 0) (1, 1, 1, 1) (0, 0, 0, 0) (1, 1, 1, 1) (0, 0, 0, 0) (1, 1, 1, 1) (1, 1, 1, 1) (0, 0, 0, 0) ready wai t ready d0 wai t ready d0 (1, 1, 1, 0) (1, 1, 1, 1) (1, 1, 1, 0) (1, 1, 1, 1) (0, 0, 0, 0) sa0 da0 sa0 + 8h (1, 1, 0) (1, 1, 0) (0, 0, 0, 0) (0, 0, 0, 0) (0, 0, 0) (0, 0, 0) d1 sa0 + 4h da0 + 4h sa0 + ch da0 + 8h da0 + ch (1, 1, 0) (0, 0, 0, 0) (0, 0, 0) (1, 1, 0) (0, 0, 0, 0) (0, 0, 0) (1, 1, 0) (0, 0, 0, 0) (0, 0, 0) (1, 1, 0) (0, 0, 0, 0) (0, 0, 0) (1, 1, 0) (0, 0, 0, 0) (0, 0, 0) (1, 1, 0) (0, 0, 0, 0) (0, 0, 0) wai t ready wai t ready wai t ready wai t ready wai t ready wai t d2 d3 d1 d2 d3 (1, 1, 1, 0) (1, 1, 1, 1) (1, 1, 1, 0) (1, 1, 1, 1) (1, 1, 1, 0) (1, 1, 1, 1) (1, 1, 1, 0) (1, 1, 1, 1) (1, 1, 1, 0) (1, 1, 1, 1) (1, 1, 1, 0) (1, 1, 1, 1) (0, 0, 0, 1) (0, 0, 0, 0) t1 t2 t1 t2 vbclk (input) busclk (output) vsa25 to vsa0 (input) vsbenz3 to vsbenz0 (input) vsctyp2 to vsctyp0 (input) vsstz (input) transfer response vbdi31 to vbdi0 (output) a25 t o a0 (output) csz7 to csz0 (output) rdzf (output) wrz3 t o wrz0 (output) bcystz (output) benz3 t o benz0 (output) dc3r to dc0r (output) di31 to di 0 (input) do31 to do0 (output) cpu core ? NA85E535 NA85E535 ? sram vdcsz7 to vdcsz0 (input) rdzr (output) vbdo31 to vbdo0 (input) dmxczm03 t o dmxczm00 (output) dc3f to dc0f (output) dmxcsz03 to dmxcsz00 (input) dmxtco03 to dmxtco00 (input) dma pins vsseq2 to vsseq0 (input) t1 t2 t1 t2 dmxtcm03 t o dmxtcm00 (output) t1 t2 t1 t2 t1 t2 t1 t2 vswrite (input) (1, 1, 1, 1) (1, 1, 1, 1)
chapter 4 memory acc ess timing examples preliminary user?s manual a15555ej2v0um 172 figure 4-20. example of dma transfer timing (2-cycle transfer (with na85e300): sram sram) (4/5) (d) single transfer (4 word)/with speculative read/local bus size: 32 bits sa0 + 4h sa0 + ch (0, 0, 0, 1) (0, 0, 0, 0) (1, 1, 1, 1) (0, 0, 0, 0) d0 (1, 1, 1, 1) (1, 1, 1, 1) (0, 0, 0, 0) (0, 0, 0, 0) (0, 0, 0, 0) sa0 sa0 + 8h (1, 1, 1, 1) (1, 1, 1, 1) (0, 0, 0, 0) da0 + 4h (0, 0, 0, 0) (1, 1, 1, 1) (1, 1, 1, 1) (0, 0, 0, 0) (1, 1, 1, 1) (1, 1, 1, 1) (0, 0, 0, 0) d0 (1, 1, 0) (0, 0, 0) (0, 0, 1) wait ready da0 d0 (1, 1, 1, 0) (1, 1, 1, 1) (0, 0, 0, 0) wait ready wait ready d0 (1, 1, 1, 0) (1, 1, 1, 1) (1, 1, 0) (0, 0, 0, 0) (0, 0, 0, 0) (0, 1, 0) (0, 0, 1) sa0 sa0 + 4h t1 t2 t1 t2 vbclk (input) busclk (output) vsa25 to vsa0 (input) vsbenz3 to vsbenz0 (input) vsctyp2 to vsctyp0 (input) vsstz (input) transfer response vbdi31 to vbdi0 (output) a25 to a0 (output) csz7 to csz0 (output) rdzf (output) wrz3 to wrz0 (output) bcystz (output) benz3 to benz0 (output) dc3r to dc0r (output) di31 to di0 (input) do31 to do0 (output) cpu core ? NA85E535 NA85E535 ? sram vdcsz7 to vdcsz0 (input) rdzr (output) vbdo31 to vbdo0 (input) dmxczm03 to dmxczm00 (output) dc3f to dc0f (output) dmxcsz03 to dmxcsz00 (input) dmxtco03 to dmxtco00 (input) dma pins vsseq2 to vsseq0 (input) t1 t2 dmxtcm03 to dmxtcm00 (output) (0, 0, 0) (0, 1, 0) (0, 0, 0) sa0 + 8h sa0 + ch da0 + 4h da0 + 8h da0 + ch wait ready wait ready d1 d2 d3 d1 d2 d3 (0, 0, 0, 1) t1 t2 t1 t2 da0 t1 t2 da0 + ch t1 t2 da0 + 8h t1 t2 (1, 1, 1, 1) (0, 0, 0, 0) (1, 1, 1, 1) (0, 0, 0, 0) d1 d2 d3 d1 d2 d3 vswrite (input)
chapter 4 memory acc ess timing examples preliminary user?s manual a15555ej2v0um 173 figure 4-20. example of dma transfer timing (2-cycle transfer (with na85e300): sram sram) (5/5) (e) single transfer (4 word)/without speculative read/local bus size: 32 bits sa0 + 4h sa0 + ch (0, 0, 0, 1) (0, 0, 0, 0) (1, 1, 1, 1) (0, 0, 0, 0) d0 (1, 1, 1, 1) (1, 1, 1, 1) (0, 0, 0, 0) (0, 0, 0, 0) (0, 0, 0, 0) sa0 sa0 + 8h (1, 1, 1, 1) da0 + 4h (0, 0, 0, 0) (1, 1, 1, 1) (1, 1, 1, 1) (0, 0, 0, 0) (1, 1, 1, 1) (1, 1, 1, 1) (0, 0, 0, 0) d0 (1, 1, 0) wait ready da0 d0 (1, 1, 1, 0) (1, 1, 1, 1) (0, 0, 0, 0) wait ready wait ready d0 (1, 1, 1, 0) (1, 1, 1, 1) (1, 1, 0) (0, 0, 0, 0) (0, 0, 0, 0) (0, 1, 0) (0, 0, 1) sa0 sa0 + 4h t1 t2 t1 t2 vbclk (input) busclk (output) vsa25 to vsa0 (input) vsbenz3 to vsbenz0 (input) vsctyp2 to vsctyp0 (input) vsstz (input) transfer response vbdi31 to vbdi0 (output) a25 to a0 (output) csz7 to csz0 (output) rdzf (output) wrz3 to wrz0 (output) bcystz (output) benz3 to benz0 (output) dc3r to dc0r (output) di31 to di0 (input) do31 to do0 (output) cpu core ? NA85E535 NA85E535 ? sram vdcsz7 to vdcsz0 (input) rdzr (output) vbdo31 to vbdo0 (input) dmxczm03 to dmxczm00 (output) dc3f to dc0f (output) dmxcsz03 to dmxcsz00 (input) dmxtco03 to dmxtco00 (input) dma pins vsseq2 to vsseq0 (input) t1 t2 dmxtcm03 to dmxtcm00 (output) (0, 0, 0) (0, 0, 0) sa0 + 8h sa0 + ch da0 + 4h da0 + 8h da0 + ch wait ready wait ready d1 d2 d3 d1 d2 d3 (0, 0, 0, 1) t1 t2 t1 t2 da0 t1 t2 da0 + ch t1 t2 da0 + 8h t1 t2 (1, 1, 1, 1) (0, 0, 0, 0) (1, 1, 1, 1) (0, 0, 0, 0) d1 d2 d3 d1 d2 d3 (0, 0, 0) (0, 1, 0) (0, 0, 0, 0) (0, 0, 0, 0) (1, 1, 1, 1) (0, 0, 0, 0) (1, 1, 1, 1) (0, 0, 0, 0) (1, 1, 1, 1) (1, 1, 1, 1) (0, 0, 0, 0) (1, 1, 1, 1) (0, 0, 0, 0) (1, 1, 1, 1) (0, 0, 0, 0) vswrite (input) (0, 0, 1)
chapter 4 memory acc ess timing examples preliminary user?s manual a15555ej2v0um 174 figure 4-21. example of dma transfer timing (2-cycle transfer (with na85e300): sdram sdram) (1/5) (a) single transfer/without wait/cl = 2/without speculative read/local bus size: 32 bits sa0 (0, 0, 0, 1) (0, 0, 0, 0) (1, 1, 1, 1) (0, 0, 0, 0) d0 (1, 1, 1, 1) (1, 1, 1, 1) (0, 0, 0, 0) (0, 0, 0, 0) (0, 0, 0, 0) d0 col (sa0) col (da0) (1, 1, 1, 1) (0, 0, 0, 0) (1, 1, 1, 1) (0, 0, 0, 0) (1, 1, 1, 1) col (sa0) col (da0) (1, 1, 1, 1) (0, 0, 0, 0) (1, 1, 1, 1) (0, 0, 0, 0) (1, 1, 1, 1) (0, 0, 0, 0) (1, 1, 1, 1) (1, 1, 1, 1) (0, 0, 0, 0) d0 (1, 1, 0) (1, 1, 0) (0, 0, 0, 0) (0, 0, 0, 0) (0, 0, 0) (0, 0, 0) wait wait ready ready d0 da0 d0 (1, 1, 1, 0) (1, 1, 1, 1) (1, 1, 1, 0) (1, 1, 1, 1) (0, 0, 0, 1) (0, 0, 0, 0) wait ready d0 wait ready d0 (1, 1, 1, 0) (1, 1, 1, 1) (1, 1, 1, 0) (1, 1, 1, 1) (0, 0, 0, 0) (1, 1, 0) (1, 1, 0) (0, 0, 0, 0) (0, 0, 0, 0) (0, 0, 0) (0, 0, 0) sa0 da0 tread tlate t0 twr vbclk (input) busclk (output) vsa25 to vsa0 (input) vsbenz3 to vsbenz0 (input) vsctyp2 to vsctyp0 (input) vsstz (input) transfer response vbdi31 to vbdi0 (output) a25 to a0 (output) csz7 to csz0 (output) sdrasz (output) sdwez (output) bcystz (output) benz3 to benz0 (output) dc3r to dc0r (output) di31 to di0 (input) do31 to do0 (output) cpu core ? NA85E535 NA85E535 ? sdram vdcsz7 to vdcsz0 (input) sdcasz (output) vbdo31 to vbdo0 (input) dmxczm03 to dmxczm00 (output) dc3f to dc0f (output) dmxcsz03 to dmxcsz00 (input) dmxtco03 to dmxtco00 (input) dma pins vsseq2 to vsseq0 (input) dmxtcm03 to dmxtcm00 (output) dqm3 to dqm0 (output) t0 tlate tread tlate t0 twr t0 tlate h (1, 1, 1, 1) (0, 0, 0, 0) (1, 1, 1, 1) (0, 0, 0, 0) (1, 1, 1, 1) (0, 0, 0, 0) (1, 1, 1, 1) (0, 0, 0, 0) (1, 1, 1, 1) d0 vswrite (input)
chapter 4 memory acc ess timing examples preliminary user?s manual a15555ej2v0um 175 figure 4-21. example of dma transfer timing (2-cycle transfer (with na85e300): sdram sdram) (2/5) (b) block transfer/with speculative read/local bus size: 32 bits (0, 0, 0, 0) (1, 1, 1, 1) (0, 0, 0, 0) (1, 1, 1, 1) d0 (1, 1, 1, 1) (0, 0, 0, 0) (0, 0, 0, 0) col (sa0) (1, 1, 1, 1) (1, 1, 1, 1) (0, 0, 0, 0) (1, 1, 1, 1) (0, 0, 0, 0) d2 (0, 0, 0, 0) (0, 0, 0, 1) (0, 0, 0, 0) (0, 0, 0, 0) (0, 0, 0, 0) (1, 1, 1, 1) (1, 1, 1, 1) (0, 0, 0, 0) (1, 1, 1, 1) (0, 0, 0, 0) (1, 1, 1, 1) (0, 0, 0, 0) d1 d3 ready da0 + ch (1, 1, 0) (0, 0, 0, 0) (0, 0, 0) wait d3 (1, 1, 1, 0) (1, 1, 1, 1) (0, 0, 0, 1) (0, 0, 0, 0) sa0 + 8h sa0 + ch da0 + 8h (1, 1, 0) (0, 0, 0, 0) (0, 0, 0) (1, 1, 0) (0, 0, 0, 0) (0, 0, 0) (1, 1, 0) (0, 0, 0, 0) (0, 0, 0) ready wait ready wait ready wait ready d2 d3 d1 d2 (1, 1, 1, 1) (1, 1, 1, 0) (1, 1, 1, 1) (1, 1, 1, 0) (1, 1, 1, 1) (1, 1, 1, 0) (1, 1, 1, 1) wait ready d0 wait ready d0 (1, 1, 1, 0) (1, 1, 1, 1) (1, 1, 1, 0) (1, 1, 1, 1) (0, 0, 0, 0) sa0 da0 (1, 1, 0) (1, 1, 0) (0, 0, 0, 0) (0, 0, 0, 0) (0, 0, 0) (0, 0, 0) d1 sa0 + 4h da0 + 4h (1, 1, 0) (0, 0, 0, 0) (0, 0, 0) (1, 1, 0) (0, 0, 0, 0) (0, 0, 0) wait ready wait (1, 1, 1, 0) (1, 1, 1, 1) (1, 1, 1, 0) tread tread tlate tw vbclk (input) busclk (output) vsa25 to vsa0 (input) vswrite (input) vsbenz3 to vsbenz0 (input) vsctyp2 to vsctyp0 (input) vsstz (input) transfer response vbdi31 to vbdi0 (output) a25 to a0 (output) csz7 to csz0 (output) sdrasz (output) dqm3 to dqm0 (output) bcystz (output) benz3 to benz0 (output) dc3r to dc0r (output) di31 to di0 (input) do31 to do0 (output) cpu core ? NA85E535 NA85E535 ? sdram sdcasz (output) vbdo31 to vbdo0 (input) dmxczm03 to dmxczm00 (output) dc3f to dc0f (output) dmxcsz03 to dmxcsz00 (input) dmxtco03 to dmxtco00 (input) dma pins vsseq2 to vsseq0 (input) t0 dmxtcm03 to dmxtcm00 (output) tread tlate twr twr sdwez (output) t0 tread t0 twr t0 twr col (da0) h (1, 1, 1, 1) (1, 1, 1, 1) (0, 0, 0, 0) (1, 1, 1, 1) (0, 0, 0, 0) (1, 1, 1, 1) (1, 1, 1, 1) (1, 1, 1, 1) (0, 0, 0, 0) (0, 0, 0, 0) (1, 1, 1, 1) (1, 1, 1, 1) d1 d0 d2 d3 vdcsz7 to vdcsz0 (input) col (sa0 + 4h) col (sa0 + 8h) col (sa0 + ch) col (da0 + 4h) col (da0 + 8h) col (da0 + ch)
chapter 4 memory acc ess timing examples preliminary user?s manual a15555ej2v0um 176 figure 4-21. example of dma transfer timing (2-cycle transfer (with na85e300): sdram sdram) (3/5) (c) block transfer/without speculative read/local bus size: 32 bits (0, 0, 0, 0) (1, 1, 1, 1) (1, 1, 1, 1) (1, 1, 1, 1) (1, 1, 1, 1) d0 (1, 1, 1, 1) (0, 0, 0, 0) (0, 0, 0, 0) d0 (0, 0, 0, 0) col (sa0) (1, 1, 1, 1) (0, 0, 0, 0) d2 (0, 0, 0, 0) (0, 0, 0, 1) (0, 0, 0, 0) col (da0) (1, 1, 1, 1) (0, 0, 0, 0) (0, 0, 0, 0) (0, 0, 0, 0) (0, 0, 0, 0) (0, 0, 0, 0) (0, 0, 0, 0) d1 d2 d3 d1 d3 (0, 0, 0, 0) (0, 0, 0, 0) (1, 1, 1, 1) (1, 1, 1, 1) (0, 0, 0, 0) (0, 0, 0, 0) (0, 0, 0, 0) (1, 1, 1, 1) (0, 0, 0, 0) (1, 1, 1, 1) (0, 0, 0, 0) (1, 1, 1, 1) (1, 1, 1, 1) (0, 0, 0, 0) ready wait ready d0 wait ready d0 (1, 1, 1, 0) (1, 1, 1, 1) (1, 1, 1, 0) (1, 1, 1, 1) (0, 0, 0, 0) sa0 da0 sa0 + 8h (1, 1, 0) (1, 1, 0) (0, 0, 0, 0) (0, 0, 0, 0) (0, 0, 0) (0, 0, 0) d1 sa0 + 4h da0 + 4h sa0 + ch da0 + 8h da0 + ch (1, 1, 0) (0, 0, 0, 0) (0, 0, 0) (1, 1, 0) (0, 0, 0, 0) (0, 0, 0) (1, 1, 0) (0, 0, 0, 0) (0, 0, 0) (1, 1, 0) (0, 0, 0, 0) (0, 0, 0) (1, 1, 0) (0, 0, 0, 0) (0, 0, 0) (1, 1, 0) (0, 0, 0, 0) (0, 0, 0) wait ready wait ready wait ready wait ready wait ready wait d2 d3 d1 d2 d3 (1, 1, 1, 0) (1, 1, 1, 1) (1, 1, 1, 0) (1, 1, 1, 1) (1, 1, 1, 0) (1, 1, 1, 1) (1, 1, 1, 0) (1, 1, 1, 1) (1, 1, 1, 0) (1, 1, 1, 1) (1, 1, 1, 0) (1, 1, 1, 1) (0, 0, 0, 1) (0, 0, 0, 0) vbclk (input) busclk (output) vsa25 to vsa0 (input) vsbenz3 to vsbenz0 (input) vsctyp2 to vsctyp0 (input) vsstz (input) transfer response vbdi31 to vbdi0 (output) a25 to a0 (output) csz7 to csz0 (output) sdrasz (output) dqm3 to dqm0 (output) bcystz (output) benz3 to benz0 (output) dc3r to dc0r (output) di31 to di0 (input) do31 to do0 (output) cpu core ? NA85E535 NA85E535 ? sdram vdcsz7 to vdcsz0 (input) sdcasz (output) vbdo31 to vbdo0 (input) dmxczm03 to dmxczm00 (output) dc3f to dc0f (output) dmxcsz03 to dmxcsz00 (input) dmxtco03 to dmxtco00 (input) dma pins vsseq2 to vsseq0 (input) dmxtcm03 to dmxtcm00 (output) sdwez (output) tread tlate twr tlate t0 t0 tread tlate twr tlate t0 t0 tread tlate twr tlate t0 t0 tread tlate twr tlate t0 t0 h (0, 0, 0, 0) (1, 1, 1, 1) (1, 1, 1, 1) (0, 0, 0, 0) (1, 1, 1, 1) (1, 1, 1, 1) (1, 1, 1, 1) (1, 1, 1, 1) (0, 0, 0, 0) (1, 1, 1, 1) (0, 0, 0, 0) (1, 1, 1, 1) (1, 1, 1, 1) (1, 1, 1, 1) (1, 1, 1, 1) (0, 0, 0, 0) (1, 1, 1, 1) (0, 0, 0, 0) (1, 1, 1, 1) (1, 1, 1, 1) (1, 1, 1, 1) vswrite (input) col (sa0 + 4h) col (sa0 + 8h) col (sa0 + ch) col (da0 + 4h) col (da0 + 8h) col (da0 + ch)
chapter 4 memory acc ess timing examples preliminary user?s manual a15555ej2v0um 177 figure 4-21. example of dma transfer timing (2-cycle transfer (with na85e300): sdram sdram) (4/5) (d) single transfer (4 words)/with speculative read/local bus size: 32 bits sa0 + 4h (0, 0, 0, 0) (1, 1, 1, 1) (0, 0, 0, 0) (1, 1, 1, 1) d0 (1, 1, 1, 1) (0, 0, 0, 0) col (sa0) (1, 1, 1, 1) (0, 0, 0, 0) (1, 1, 1, 1) d1 (0, 0, 0, 1) (0, 0, 0, 0) (1, 1, 1, 1) wait ready d0 (1, 1, 1, 0) (1, 1, 1, 1) sa0 sa0 + 8h (1, 1, 0) (1, 1, 0) (0, 0, 0, 0) (0, 0, 0, 0) (0, 1, 0) (0, 1, 0) da0 da0 + 4h (0, 0, 1) wait ready (1, 1, 1, 0) tread tread tlate tw vbclk (input) busclk (output) vsa25 to vsa0 (input) vsbenz3 to vsbenz0 (input) vsctyp2 to vsctyp0 (input) vsstz (input) transfer response vbdi31 to vbdi0 (output) a25 to a0 (output) csz7 to csz0 (output) sdrasz (output) dqm3 to dqm0 (output) bcystz (output) benz3 to benz0 (output) dc3r to dc0r (output) di31 to di0 (input) do31 to do0 (output) cpu core ? NA85E535 NA85E535 ? sdram vdcsz7 to vdcsz0 (input) sdcasz (output) vbdo31 to vbdo0 (input) dmxczm03 to dmxczm00 (output) dc3f to dc0f (output) dmxcsz03 to dmxcsz00 (input) dmxtco03 to dmxtco00 (input) dma pins vsseq2 to vsseq0 (input) t0 dmxtcm03 to dmxtcm00 (output) tread tlate twr twr sa0 + ch sdwez (output) t0 tread twr twr col (da0) h (0, 0, 0, 0) (1, 1, 1, 1) (1, 1, 1, 1) (1, 1, 1, 1) (0, 0, 0, 0) (0, 0, 0, 0) (1, 1, 1, 1) (1, 1, 1, 1) d2 d3 da0 + 8h da0 + ch (0, 0, 1) (0, 0, 0) (0, 0, 0) d1 d2 d3 d0 d1 d2 d3 (0, 0, 0, 0) (0, 0, 0, 1) (0, 0, 0, 0) d0 d1 d2 d3 vswrite (input) col (sa0 + 4h) col (sa0 + 8h) col (sa0 + ch) col (da0 + 4h) col (da0 + 8h) col (da0 + ch)
chapter 4 memory acc ess timing examples preliminary user?s manual a15555ej2v0um 178 figure 4-21. example of dma transfer timing (2-cycle transfer (with na85e300): sdram sdram) (5/5) (e) single transfer (4 words)/without speculative read/local bus size: 32 bits sa0 + 4h (0, 0, 0, 0) (1, 1, 1, 1) (0, 0, 0, 0) (1, 1, 1, 1) d0 (1, 1, 1, 1) (0, 0, 0, 0) col (sa0) (1, 1, 1, 1) (0, 0, 0, 0) (1, 1, 1, 1) d1 (0, 0, 0, 1) (0, 0, 0, 0) (1, 1, 1, 1) wait ready d0 (1, 1, 1, 0) (1, 1, 1, 1) sa0 sa0 + 8h (1, 1, 0) (1, 1, 0) (0, 0, 0, 0) (0, 0, 0, 0) (0, 1, 0) (0, 1, 0) da0 da0 + 4h (0, 0, 1) wait ready (1, 1, 1, 0) tread tread tlate tw vbclk (input) busclk (output) vsa25 to vsa0 (input) vsbenz3 to vsbenz0 (input) vsctyp2 to vsctyp0 (input) vsstz (input) transfer response vbdi31 to vbdi0 (output) a25 to a0 (output) csz7 to csz0 (output) sdrasz (output) dqm3 to dqm0 (output) bcystz (output) benz3 to benz0 (output) dc3r to dc0r (output) di31 to di0 (input) do31 to do0 (output) cpu core ? NA85E535 NA85E535 ? sdram vdcsz7 to vdcsz0 (input) sdcasz (output) vbdo31 to vbdo0 (input) dmxczm03 to dmxczm00 (output) dc3f to dc0f (output) dmxcsz03 to dmxcsz00 (input) dmxtco03 to dmxtco00 (input) dma pins vsseq2 to vsseq0 (input) t0 dmxtcm03 to dmxtcm00 (output) tread tlate twr twr sa0 + ch sdwez (output) t0 tread twr twr col (da0) h (0, 0, 0, 0) (1, 1, 1, 1) (1, 1, 1, 1) (1, 1, 1, 1) (0, 0, 0, 0) (0, 0, 0, 0) (1, 1, 1, 1) (1, 1, 1, 1) d2 d3 da0 + 8h da0 + ch (0, 0, 1) (0, 0, 0) (0, 0, 0) d1 d2 d3 d0 d1 d2 d3 (0, 0, 0, 0) (0, 0, 0, 1) (0, 0, 0, 0) d0 d1 d2 d3 vswrite (input) col (sa0 + 4h) col (sa0 + 8h) col (sa0 + ch) col (da0 + 4h) col (da0 + 8h) col (da0 + ch)
chapter 4 memory acc ess timing examples preliminary user?s manual a15555ej2v0um 179 figure 4-22. sdram cbr refresh timing vsa25 to vsa0 (input) vbclk (input) busclk (output) trpw trpw trpw trpw allpre refw refw refw tref refw vbdi31 to vbdi0 (output) vdcsz (input) cke (output) csz7 to csz0 (output) dqm3 to dqm0 (output) a25, a24, a21 to a13 (output) a23, a22 (output) a12 note (output) a11 to a2 (output) sdrasz (output) sdcasz (output) sdwez (output) all bank precharge command vacbrrq (output) vaack (input) trpw h h refresh command bcw 4clk refw refw refw trpw trpw trpw trpw trpw cpu core ? NA85E535 NA85E535 ? sdram vbdo31 to vbdo0 (input) refresh counter match timing refrqz (output) vmlock (output) note this is the case where the local bus size is 32 bits. read the local bus size of 16 bits or 8 bits as ?a11? or ?a10?, respecti vely. remark a trpw state is inserted while the NA85E535 is waiting for generation of a cycle. if no cycle is generated, the NA85E535 is al ways in the trpw state. in figures 4-22 and 4-23, it is in trpw state while it is arbitrating the vsb.
chapter 4 memory acc ess timing examples preliminary user?s manual a15555ej2v0um 180 figure 4-23. sdram self-refresh timing (stop timing) vbclk (input) busclk (output) trpw trpw trpw trpw allpre refw refw refw tref refw refw vbdo31 to vbdo0 (input) cke (output) csz7 to csz0 (output) dqm3 to dqm0 (output) a25, a24, a21 to a13 (output) a23, a22 (output) a12 not e (output) a11 to a2 (output) sdrasz (output) sdcasz (output) sdwez (output) all bank precharge command vaexreq (output) vaack (input) trpw h nop command vdcsz (input) stprq (input) stpak (output) refresh command refw refw refw trpw bcw 4clk refw trpw trpw trpw trpw trpw cpu core ? NA85E535 NA85E535 ? sdram vbdi31 to vbdi0 (output) refrqz (output) nop command self-refresh mode vmlock (output) note this is the case where the local bus size is 32 bits. read the local bus size of 16 bits or 8 bits as ?a11? or ?a10?, respecti vely.
chapter 4 memory acc ess timing examples preliminary user?s manual a15555ej2v0um 181 figure 4-24. mobileram deep power down timing (stop timing) vbclk (input) busclk (output) trpw trpw trpw trpw allpre refw refw refw tref refw refw vbdo31 to vbdo0 (input) cke (output) csz7 to csz0 (output) dqm3 to dqm0 (output) a25, a24, a21 to a13 (output) a23, a22 (output) a12 note (output) a11 to a2 (output) sdrasz (output) sdcasz (output) sdwez (output) all bank precharge command vaexreq (output) vaack (input) trpw h nop command vdcsz (input) stprq (input) stpak (output) deep power down command refw refw refw trpw bcw 4clk refw trpw trpw trpw trpw trpw cpu core ? NA85E535 NA85E535 ? mobileram vbdi31 to vbdi0 (output) refrqz (output) nop command deep power down mode vmlock (output) h note this is the case where the local bus size is 32 bits. read the local bus size of 16 bits or 8 bits as ?a11? or ?a10?, respecti vely.
chapter 4 memory acc ess timing examples preliminary user?s manual a15555ej2v0um 182 figure 4-25. sdram mode register write operation timing vsa25 to vsa0 (input) vbclk (input) busclk (output) vsstz (i nput) tw0 tw0 tw0 vacbrrq (output) vaack (i nput) vbdi31 to vbdi0 (output) cke (output) csz7 to csz0 (output) dqm3 to dqm0 (output) (output) a23, a22 (output) a12 note (output) a11 to a2 (output) sdrasz (output) sdcasz (output) sdwez (output) h vdcsz (input) vswrite (input) vpstb (output) tw0 tw0 allpre refw refw refw tref refw refw refw refw tref refw refw refw regw trpw trpw trpw trpw trpw valid end of refresh (first time) refresh command (second time) refersh 7 mode register write command sdram access enable end of refresh (eighth time) refresh interval 1/2 tw0 tw0 tw0 refresh command (first time) h cpu core ? NA85E535 NA85E535 ? sdram scrn register write a25, a24, a21 to a13 all bank precharge command vmlock (output) note this is the case where the local bus size is 32 bits. read the local bus size of 16 bits or 8 bits as ?a11? or ?a10?, respecti vely. vpstb (i nput)
chapter 4 memory acc ess timing examples preliminary user?s manual a15555ej2v0um 183 figure 4-26. mobileram expansion mode register write timing vsa25 to vsa0 (input) vbclk (input) busclk (output) vsstz (input) tw0 tw0 tw0 vacbrrq (output) vaack (input) vbdi31 to vbdi0 (output) cke (output) csz7 to csz0 (output) dqm3 to dqm0 (output) (output) a23, a22 (output) a12 note (output) a11 to a2 (output) sdrasz (output) sdcasz (output) sdwez (output) h vdcsz (input) vswrite (input) vpstb (input) tw0 tw0 allpre refw refw refw tref refw refw refw refw tref refw refw refw regw trpw trpw trpw trpw trpw valid end of refresh (first time) refresh command (second time) refresh 7 mode register write command mobileram access enable end of refresh (eighth time) refresh interval 1/2 tw0 tw0 tw0 refresh command (first time) h cpu core ? NA85E535 NA85E535 ? mobileram scrn register write a25, a24, a21 to a13 all bank precharge command vmlock (output) valid (1, 0) expansion mode register write command trpw trpw note this is the case where the local bus size is 32 bits. read the local bus size of 16 bits or 8 bits as ?a11? or ?a10?, respecti vely.
chapter 4 memory acc ess timing examples preliminary user?s manual a15555ej2v0um 184 figure 4-27. bmc register change timing (divided by 1 divided by 2) vpa13 to vpa0 (input) vbclk (input) vpretr (output) vpdw15 to vpdw0 (input) dc3f to dc0f (output) rdzf (output) dc3r to dc0r (output) vpwrite (input) vpubenz (input) a25 to a0 (output) rdzr (output) wrz3 to wrz0 (output) di31 to di0 (input) vsa25 to vsa0 (input) vsstz (input) vpstb (input) cz7 to csz0 (output) busclk (output) 3fff498h 0010000h 3498h 0002h within vbclk 12 clocks vbclk 12 clocks 0010000h 0h 0h feh fh 0h ffh h h
chapter 4 memory acc ess timing examples preliminary user?s manual a15555ej2v0um 185 figure 4-28. example of sram write access timing (if vbclk is divided by two to generate busclk) d0 ready (1, 1, 1, 1) d1 wait ready wait wrstbz (output) vbclk (input) transfer response vbdo31 to vbdo0 (input) vsbenz3 to vsbenz0 (input) vsctyp2 to vsctyp0 (input) vswrite (input) vsstz (input) vsa25 to vsa0 (input) vdcsz7 to vdcsz0 (input) cpu core ? NA85E535 a25 to a0 (output) csz7 to csz0 (output) rdzf, rdzr (output) wrz3 to wrz0 (output) bcystz (output) benz3 to benz0 (output) dc3r to dc0r (output) do31 to do0 (output) waitz (input) NA85E535 ? sram h dc3f to dc0f (output) (0, 0, 0, 0) (0, 0, 0, 0) (1, 1, 1, 1) d0 busclk (output) t0 (1, 1, 1, 1) (1, 1, 1, 1) d1 (1, 1, 1, 1) t1 t2 ta t1 tw t2 remark the output timing of the do31 to do0 signals differs compared with when the vbclk signal is divided by one to generate busclk.
preliminary user?s manual a15555ej20um 186 chapter 5 test function 5.1 separate unit test to test the internal circuitry of the NA85E535, set the separate unit test mode by inputting a high level to the test and bunri pins, and conduct the test by using the test input pins (tbi19 to tbi0) and test output pins (tbo15 to tbo0). 5.2 notes on wiring test bus the NA85E535 does not initialize the normally connected pins in the separation test mode of other macros (bunri = 1, test = 0). if the vdcszn signal is active at this time, an active level is output to the vswait pin (n = 7 to 0). the cpu core has a peripheral test mode that tests the macro connected to its vsb (npb) via the test bus. in this peripheral test mode, the vsb pin is valid even in the test bus mode. therefore, the test pattern of the vsb peripheral macro may not pass because of the output pin level of the NA85E535 in the vsb peripheral test mode using the test bus of the cpu core. to avoid this, wire the tbi3 and test signals of the test bus of the NA85E535 as shown in figure 5-1 after wiring the test bus with testact. note that this wiring is not necessary if there is no macro to be tested in the peripheral test mode using the test bus of the cpu core. figure 5-1. wiring of test bus bunri test tbi3 NA85E535 tbi3 vswait test (selects NA85E535) bunriout pin of cpu core to vmwait pin of vsb bus master to vpdi15 to vpdi0 pins of cpu core vpdr15 to vpdr0 remark the tbi19 to tbi4, tbi2 to tbi0, and tbo15 to tbo0 pins require no special processing.
preliminary user?s manual a15555ej2v0um 187 chapter 6 data flow the flow to transfer data to the external memory differs depending on the set values of the registers, start address, and data width. figure 6-1. data, vsb, external data bus do31 to do0 di31 to di0 vbdo31 to vbdo0 vbdi31 to vbdi0 d (external data bus) 8/16/32 bits v (vsb) fixed to 32 bits b/hw/w NA85E535 bus master external memory b/hw/w remark b: byte data hw: halfword data w: word data the data flow in each condition is shown on the following pages.
chapter 6 data flow preliminary user?s manual a15555ej2v0um 188 6.1 data flow for byte access (8 bits) figure 6-2. data flow for byte access (little endian) data transfer flow address to be accessed external data bus: 32 bits external data bus: 16 bits external data bus: 8 bits 4n 4n v 0 7 8 15 16 23 24 31 d 0 7 8 15 16 23 24 31 address b 0 7 4n v 0 7 8 15 16 23 24 31 d 0 7 8 15 address b 0 7 4n v 0 7 8 15 16 23 24 31 d 0 7 address b 0 7 4n+1 v 0 7 8 15 16 23 24 31 b 0 7 d 0 7 8 15 16 23 24 31 address 4n+1 v 0 7 8 15 16 23 24 31 b 0 7 d 0 7 8 15 address 4n+1 v 0 7 8 15 16 23 24 31 b 0 7 d 0 7 address 4n+1 4n+2 v 0 7 8 15 16 23 24 31 b 0 7 d 0 7 8 15 16 23 24 31 address 4n+2 4n+2 v 0 7 8 15 16 23 24 31 d 0 7 8 15 address b 0 7 4n+2 v 0 7 8 15 16 23 24 31 d 0 7 address b 0 7 4n+3 v 0 7 8 15 16 23 24 31 b 0 7 d 0 7 8 15 16 23 24 31 address 4n+3 v 0 7 8 15 16 23 24 31 b 0 7 d 0 7 8 15 address 4n+3 v 0 7 8 15 16 23 24 31 b 0 7 d 0 7 address 4n+3 remarks 1. b: byte data, v: vsb (fixed to 32 bits), d: external data bus 2. solid line ( ): write dotted line ( ): read 3. n = 0, 1, 2, 3, ?
chapter 6 data flow preliminary user?s manual a15555ej2v0um 189 figure 6-3. data flow for byte access (big endian) data transfer flow address to be accessed external data bus: 32 bits external data bus: 16 bits external data bus: 8 bits 4n v 0 7 8 15 16 23 24 31 d 0 7 8 15 16 23 24 31 address b 0 7 4n v 0 7 8 15 16 23 24 31 b 0 7 d 0 7 8 15 4n address v 0 7 8 15 16 23 24 31 b 0 7 d 0 7 4n address 4n+1 v 0 7 8 15 16 23 24 31 b 0 7 d 0 7 8 15 16 23 24 31 address 4n+1 4n+1 v 0 7 8 15 16 23 24 31 d 0 7 8 15 b 0 7 address 4n+1 v 0 7 8 15 16 23 24 31 d 0 7 b 0 7 address 4n+2 v 0 7 8 15 16 23 24 31 b 0 7 d 0 7 8 15 16 23 24 31 address 4n+2 v 0 7 8 15 16 23 24 31 b 0 7 d 0 7 8 15 address 4n+2 v 0 7 8 15 16 23 24 31 b 0 7 d 0 7 address 4n+2 4n+3 v 0 7 8 15 16 23 24 31 b 0 7 d 0 7 8 15 16 23 24 31 address 4n+3 v 0 7 8 15 16 23 24 31 b 0 7 d 0 7 address 4n+3 8 15 v 0 7 8 15 16 23 24 31 b 0 7 d 0 7 address 4n+3 remarks 1. b: byte data, v: vsb (fixed to 32 bits), d: external data bus 2. solid line ( ): write dotted line ( ): read 3. n = 0, 1, 2, 3, ?
chapter 6 data flow preliminary user?s manual a15555ej2v0um 190 6.2 data flow for halfword access (16 bits) figure 6-4. data flow for halfword access (little endian) (1/3) (a) external data bus: 32 bits data transfer flow (number of transfers when viewed from external bus) address to be accessed first time second time 4n v 0 7 8 15 16 23 24 31 hw 0 7 d 0 7 8 15 16 23 24 31 address 4n+1 4n 8 15 ? 4n+1 v 0 7 8 15 16 23 24 31 hw 0 7 d 0 7 8 15 16 23 24 31 address 4n+1 8 15 v 0 7 8 15 16 23 24 31 hw 0 7 d 0 7 8 15 16 23 24 31 address 4n+2 8 15 4n+2 v 0 7 8 15 16 23 24 31 hw 0 7 d 0 7 8 15 16 23 24 31 address 4n+2 8 15 4n+3 ? 4n+3 v 0 7 8 15 16 23 24 31 hw 0 7 d 0 7 8 15 16 23 24 31 address 8 15 4n+3 v 0 7 8 15 16 23 24 31 hw 0 7 d 0 7 8 15 16 23 24 31 address 8 15 4n+4 remarks 1. b: byte data, v: vsb (fixed to 32 bits), d: external data bus 2. solid line ( ): write dotted line ( ): read 3. n = 0, 1, 2, 3, ?
chapter 6 data flow preliminary user?s manual a15555ej2v0um 191 figure 6-4. data flow for halfword access (little endian) (2/3) (b) external data bus: 16 bits data transfer flow (number of transfers when viewed from external bus) address to be accessed first time second time 4n v 0 7 8 15 16 23 24 31 hw 0 7 d 0 7 8 15 address 4n+1 4n 8 15 ? 4n+1 v 0 7 8 15 16 23 24 31 hw 0 7 d 0 7 8 15 address 4n+1 8 15 v 0 7 8 15 16 23 24 31 hw 0 7 d 0 7 8 15 address 4n+2 8 15 4n+2 v 0 7 8 15 16 23 24 31 hw 0 7 d 0 7 8 15 address 4n+2 8 15 4n+3 ? 4n+3 v 0 7 8 15 16 23 24 31 hw 0 7 d 0 7 8 15 address 8 15 4n+3 v 0 7 8 15 16 23 24 31 hw 0 7 d 0 7 8 15 address 8 15 4n+4 remarks 1. b: byte data, v: vsb (fixed to 32 bits), d: external data bus 2. solid line ( ): write dotted line ( ): read 3. n = 0, 1, 2, 3, ?
chapter 6 data flow preliminary user?s manual a15555ej2v0um 192 figure 6-4. data flow for halfword access (little endian) (3/3) (c) external data bus: 8 bits data transfer flow (number of transfers when viewed from external bus) address to be accessed first time second time 4n v 0 7 8 15 16 23 24 31 hw 0 7 d 0 7 address 4n 8 15 v 0 7 8 15 16 23 24 31 hw 0 7 d 0 7 address 4n ? 1 8 15 4n+1 v 0 7 8 15 16 23 24 31 hw 0 7 d 8 15 0 7 address 4n ? 1 v 0 7 8 15 16 23 24 31 hw 0 7 d 8 15 0 7 address 4n ? 2 4n+2 v 0 7 8 15 16 23 24 31 hw 0 7 d 0 7 address 4n+2 8 15 v 0 7 8 15 16 23 24 31 hw 0 7 d 0 7 address 4n+3 8 15 4n+3 v 0 7 8 15 16 23 24 31 hw 0 7 d 0 7 address 8 15 4n+3 v 0 7 8 15 16 23 24 31 hw 0 7 d 0 7 address 8 15 4n+4 remarks 1. b: byte data, v: vsb (fixed to 32 bits), d: external data bus 2. solid line ( ): write dotted line ( ): read 3. n = 0, 1, 2, 3, ?
chapter 6 data flow preliminary user?s manual a15555ej2v0um 193 figure 6-5. data flow for halfword access (big endian) (1/3) (a) external data bus: 32 bits data transfer flow (number of transfers when viewed from external bus) address to be accessed first time second time 4n v 0 7 8 15 16 23 24 31 hw 0 7 d 0 7 8 15 16 23 24 31 address 4n+1 8 15 4n ? 4n+1 v 0 7 8 15 16 23 24 31 hw 0 7 d 0 7 8 15 16 23 24 31 address 8 15 4n+1 v 0 7 8 15 16 23 24 31 hw 0 7 d 0 7 8 15 16 23 24 31 address 8 15 4n+2 4n+2 v 0 7 8 15 16 23 24 31 hw 0 7 d 0 7 8 15 16 23 24 31 address 4n+2 4n+3 8 15 ? 4n+3 v 0 7 8 15 16 23 24 31 hw 0 7 d 0 7 8 15 16 23 24 31 address 4n+3 8 15 v 0 7 8 15 16 23 24 31 hw 0 7 d 0 7 8 15 16 23 24 31 address 4n+4 8 15 remarks 1. b: byte data, v: vsb (fixed to 32 bits), d: external data bus 2. solid line ( ): write dotted line ( ): read 3. n = 0, 1, 2, 3, ?
chapter 6 data flow preliminary user?s manual a15555ej2v0um 194 figure 6-5. data flow for halfword access (big endian) (2/3) (b) external data bus: 16 bits data transfer flow (number of transfers when viewed from external bus) address to be accessed first time second time 4n v 0 7 8 15 16 23 24 31 hw 0 7 d 0 7 8 15 address 4n+1 8 15 4n ? 4n+1 v 0 7 8 15 16 23 24 31 hw 0 7 d 0 7 8 15 address 4n+1 8 15 v 0 7 8 15 16 23 24 31 hw 0 7 d 0 7 8 15 address 4n+2 8 15 4n+2 v 0 7 8 15 16 23 24 31 hw 0 7 d 0 7 8 15 address 4n+2 4n+3 8 15 ? 4n+3 v 0 7 8 15 16 23 24 31 hw 0 7 d 0 7 8 15 address 4n+3 8 15 v 0 7 8 15 16 23 24 31 hw 0 7 d 0 7 8 15 address 4n+4 8 15 remarks 1. b: byte data, v: vsb (fixed to 32 bits), d: external data bus 2. solid line ( ): write dotted line ( ): read 3. n = 0, 1, 2, 3, ?
chapter 6 data flow preliminary user?s manual a15555ej2v0um 195 figure 6-5. data flow for halfword access (big endian) (3/3) (c) external data bus: 8 bits data transfer flow (number of transfers when viewed from external bus) address to be accessed first time second time 4n v 0 7 8 15 16 23 24 31 hw 0 7 d 0 7 address 8 15 4n v 0 7 8 15 16 23 24 31 hw 0 7 d 0 7 address 8 15 4n+1 4n+1 v 0 7 8 15 16 23 24 31 hw 0 7 d 0 7 address 4n+1 8 15 v 0 7 8 15 16 23 24 31 hw 0 7 d 0 7 address 4n+2 8 15 4n+2 v 0 7 8 15 16 23 24 31 hw 0 7 8 15 d 0 7 address 4n+2 v 0 7 8 15 16 23 24 31 hw 0 7 8 15 d 0 7 address 4n+3 4n+3 v 0 7 8 15 16 23 24 31 hw 0 7 d 0 7 address 4n+3 8 15 v 0 7 8 15 16 23 24 31 hw 0 7 d 0 7 address 4n+4 8 15 remarks 1. b: byte data, v: vsb (fixed to 32 bits), d: external data bus 2. solid line ( ): write dotted line ( ): read 3. n = 0, 1, 2, 3, ?
chapter 6 data flow preliminary user?s manual a15555ej2v0um 196 6.3 data flow for word access (32 bits) figure 6-6. data flow for word access (little endian) (1/3) (a) external data bus: 32 bits data transfer flow (number of transfers when viewed from external bus) address to be accessed first time second time third time 4n v 0 7 8 15 16 23 24 31 w 0 7 d 0 7 8 15 16 23 24 31 address 4n+2 8 15 4n+3 16 23 24 31 4n+1 4n ?? 4n+1 v 0 7 8 15 16 23 24 31 w 0 7 d 0 7 8 15 16 23 24 31 address 8 15 4n+1 16 23 24 31 v 0 7 8 15 16 23 24 31 w 0 7 d 0 7 8 15 16 23 24 31 address 8 15 16 23 24 31 4n+3 4n+2 v 0 7 8 15 16 23 24 31 w 0 7 d 0 7 8 15 16 23 24 31 address 8 15 4n+4 16 23 24 31 4n+2 v 0 7 8 15 16 23 24 31 w 0 7 d 0 7 8 15 16 23 24 31 address 8 15 16 23 24 31 4n+3 4n+2 v 0 7 8 15 16 23 24 31 w 0 7 d 0 7 8 15 16 23 24 31 address 8 15 16 23 24 31 4n+5 4n+4 ? 4n+3 v 0 7 8 15 16 23 24 31 w 0 7 d 0 7 8 15 16 23 24 31 address 8 15 16 23 24 31 4n+3 v 0 7 8 15 16 23 24 31 w 0 7 d 0 7 8 15 16 23 24 31 address 8 15 16 23 24 31 4n+5 4n+4 v 0 7 8 15 16 23 24 31 w 0 7 d 0 7 8 15 16 23 24 31 address 8 15 16 23 24 31 4n+6 remarks 1. b: byte data, v: vsb (fixed to 32 bits), d: external data bus 2. solid line ( ): write dotted line ( ): read 3. n = 0, 1, 2, 3, ?
chapter 6 data flow preliminary user?s manual a15555ej2v0um 197 figure 6-6. data flow for word access (little endian) (2/3) (b) external data bus: 16 bits data transfer flow (number of transfers when viewed from external bus) address to be accessed first time second time third time 4n v 0 7 8 15 16 23 24 31 w 0 7 d 0 7 8 15 4n+1 4n 8 15 address 16 23 24 31 v 0 7 8 15 16 23 24 31 w 0 7 d 0 7 8 15 4n+3 4n+2 8 15 address 16 23 24 31 ? 4n+1 v 0 7 8 15 16 23 24 31 w 0 7 d 0 7 8 15 4n+1 8 15 address 16 23 24 31 v 0 7 8 15 16 23 24 31 w 0 7 d 0 7 8 15 4n+3 8 15 address 16 23 24 31 4n+2 v 0 7 8 15 16 23 24 31 w 0 7 d 0 7 8 15 8 15 address 16 23 24 31 4n+4 4n+2 v 0 7 8 15 16 23 24 31 w 0 7 d 0 7 8 15 4n+3 4n+2 8 15 address 16 23 24 31 v 0 7 8 15 16 23 24 31 w 0 7 d 0 7 8 15 4n+5 4n+4 8 15 address 16 23 24 31 ? 4n+3 v 0 7 8 15 16 23 24 31 w 0 7 d 0 7 8 15 4n+3 8 15 address 16 23 24 31 v 0 7 8 15 16 23 24 31 w 0 7 d 0 7 8 15 4n+5 8 15 address 16 23 24 31 4n+4 v 0 7 8 15 16 23 24 31 w 0 7 d 0 7 8 15 8 15 address 16 23 24 31 4n+6 remarks 1. b: byte data, v: vsb (fixed to 32 bits), d: external data bus 2. solid line ( ): write dotted line ( ): read 3. n = 0, 1, 2, 3, ?
chapter 6 data flow preliminary user?s manual a15555ej2v0um 198 figure 6-6. data flow for word access (little endian) (3/3) (c) external data bus: 8 bits data transfer flow (number of transfers when viewed from external bus) address to be accessed first time second time third time fourth time 4n 4n v 0 7 8 15 16 23 24 31 d 0 7 w 0 7 8 15 address 16 23 24 31 4n+1 v 0 7 8 15 16 23 24 31 d 0 7 w 0 7 address 8 15 16 23 24 31 4n+2 v 0 7 8 15 16 23 24 31 d 0 7 w 0 7 address 8 15 16 23 24 31 4n+3 v 0 7 8 15 16 23 24 31 d 0 7 w 0 7 address 8 15 16 23 24 31 4n+1 4n+1 v 0 7 8 15 16 23 24 31 d 0 7 w 0 7 8 15 address 16 23 24 31 4n+2 v 0 7 8 15 16 23 24 31 d 0 7 w 0 7 address 8 15 16 23 24 31 4n+3 v 0 7 8 15 16 23 24 31 d 0 7 w 0 7 address 8 15 16 23 24 31 4n+4 v 0 7 8 15 16 23 24 31 d 0 7 w 0 7 address 8 15 16 23 24 31 4n+2 4n+2 v 0 7 8 15 16 23 24 31 d 0 7 w 0 7 8 15 address 16 23 24 31 4n+3 v 0 7 8 15 16 23 24 31 d 0 7 w 0 7 address 8 15 16 23 24 31 4n+4 v 0 7 8 15 16 23 24 31 d 0 7 w 0 7 address 8 15 16 23 24 31 4n+5 v 0 7 8 15 16 23 24 31 d 0 7 w 0 7 address 8 15 16 23 24 31 4n+3 4n+3 v 0 7 8 15 16 23 24 31 d 0 7 w 0 7 8 15 address 16 23 24 31 4n+4 v 0 7 8 15 16 23 24 31 d 0 7 w 0 7 address 8 15 16 23 24 31 4n+5 v 0 7 8 15 16 23 24 31 d 0 7 w 0 7 address 8 15 16 23 24 31 4n+6 v 0 7 8 15 16 23 24 31 d 0 7 w 0 7 address 8 15 16 23 24 31 remarks 1. b: byte data, v: vsb (fixed to 32 bits), d: external data bus 2. solid line ( ): write dotted line ( ): read 3. n = 0, 1, 2, 3, ?
chapter 6 data flow preliminary user?s manual a15555ej2v0um 199 figure 6-7. data flow for word access (big endian) (1/3) (a) external data bus: 32 bits data transfer flow (number of transfers when viewed from external bus) address to be accessed first time second time third time 4n v 0 7 8 15 16 23 24 31 w 0 7 d 0 7 8 15 16 23 24 31 address 4n+1 8 15 4n 16 23 24 31 4n+2 4n+3 ?? 4n+1 v 0 7 8 15 16 23 24 31 w 0 7 d 0 7 8 15 16 23 24 31 address 8 15 4n+1 16 23 24 31 v 0 7 8 15 16 23 24 31 w 0 7 d 0 7 8 15 16 23 24 31 address 8 15 16 23 24 31 4n+2 4n+3 v 0 7 8 15 16 23 24 31 w 0 7 d 0 7 8 15 16 23 24 31 address 8 15 4n+4 16 23 24 31 4n+2 v 0 7 8 15 16 23 24 31 w 0 7 d 0 7 8 15 16 23 24 31 address 8 15 16 23 24 31 4n+2 4n+3 v 0 7 8 15 16 23 24 31 w 0 7 d 0 7 8 15 16 23 24 31 address 8 15 16 23 24 31 4n+5 4n+4 ? 4n+3 v 0 7 8 15 16 23 24 31 w 0 7 d 0 7 8 15 16 23 24 31 address 8 15 16 23 24 31 4n+3 v 0 7 8 15 16 23 24 31 w 0 7 d 0 7 8 15 16 23 24 31 address 8 15 16 23 24 31 4n+4 4n+5 v 0 7 8 15 16 23 24 31 w 0 7 d 0 7 8 15 16 23 24 31 address 8 15 16 23 24 31 4n+6 remarks 1. b: byte data, v: vsb (fixed to 32 bits), d: external data bus 2. solid line ( ): write dotted line ( ): read 3. n = 0, 1, 2, 3, ?
chapter 6 data flow preliminary user?s manual a15555ej2v0um 200 figure 6-7. data flow for word access (big endian) (2/3) (b) external data bus: 16 bits data transfer flow (number of transfers when viewed from external bus) address to be accessed first time second time third time 4n v 0 7 8 15 16 23 24 31 w 0 7 d 0 7 8 15 4n 4n+1 8 15 address 16 23 24 31 v 0 7 8 15 16 23 24 31 w 0 7 d 0 7 8 15 4n+2 4n+3 8 15 address 16 23 24 31 ? 4n+1 v 0 7 8 15 16 23 24 31 w 0 7 d 0 7 8 15 4n+1 8 15 address 16 23 24 31 v 0 7 8 15 16 23 24 31 w 0 7 d 0 7 8 15 4n+2 8 15 address 16 23 24 31 4n+3 v 0 7 8 15 16 23 24 31 w 0 7 d 0 7 8 15 8 15 address 16 23 24 31 4n+4 4n+2 v 0 7 8 15 16 23 24 31 w 0 7 d 0 7 8 15 4n+2 4n+3 8 15 address 16 23 24 31 v 0 7 8 15 16 23 24 31 w 0 7 d 0 7 8 15 4n+4 4n+5 8 15 address 16 23 24 31 ? 4n+3 v 0 7 8 15 16 23 24 31 w 0 7 d 0 7 8 15 4n+3 8 15 address 16 23 24 31 v 0 7 8 15 16 23 24 31 w 0 7 d 0 7 8 15 4n+4 8 15 address 16 23 24 31 4n+5 v 0 7 8 15 16 23 24 31 w 0 7 d 0 7 8 15 8 15 address 16 23 24 31 4n+6 remarks 1. b: byte data, v: vsb (fixed to 32 bits), d: external data bus 2. solid line ( ): write dotted line ( ): read 3. n = 0, 1, 2, 3, ?
chapter 6 data flow preliminary user?s manual a15555ej2v0um 201 figure 6-7. data flow for word access (big endian) (3/3) (c) external data bus: 8 bits data transfer flow (number of transfers when viewed from external bus) address to be accessed first time second time third time fourth time 4n 4n v 0 7 8 15 16 23 24 31 d 0 7 w 0 7 8 15 address 16 23 24 31 4n+1 v 0 7 8 15 16 23 24 31 d 0 7 w 0 7 address 8 15 16 23 24 31 4n+2 v 0 7 8 15 16 23 24 31 d 0 7 w 0 7 address 8 15 16 23 24 31 4n+3 v 0 7 8 15 16 23 24 31 d 0 7 w 0 7 address 8 15 16 23 24 31 4n+1 4n+1 v 0 7 8 15 16 23 24 31 d 0 7 w 0 7 8 15 address 16 23 24 31 4n+2 v 0 7 8 15 16 23 24 31 d 0 7 w 0 7 address 8 15 16 23 24 31 4n+3 v 0 7 8 15 16 23 24 31 d 0 7 w 0 7 address 8 15 16 23 24 31 4n+4 v 0 7 8 15 16 23 24 31 d 0 7 w 0 7 address 8 15 16 23 24 31 4n+2 4n+2 v 0 7 8 15 16 23 24 31 d 0 7 w 0 7 8 15 address 16 23 24 31 4n+3 v 0 7 8 15 16 23 24 31 d 0 7 w 0 7 address 8 15 16 23 24 31 4n+4 v 0 7 8 15 16 23 24 31 d 0 7 w 0 7 address 8 15 16 23 24 31 4n+5 v 0 7 8 15 16 23 24 31 d 0 7 w 0 7 address 8 15 16 23 24 31 4n+3 4n+3 v 0 7 8 15 16 23 24 31 d 0 7 w 0 7 8 15 address 16 23 24 31 4n+4 v 0 7 8 15 16 23 24 31 d 0 7 w 0 7 address 8 15 16 23 24 31 4n+5 v 0 7 8 15 16 23 24 31 d 0 7 w 0 7 address 8 15 16 23 24 31 4n+6 v 0 7 8 15 16 23 24 31 d 0 7 w 0 7 address 8 15 16 23 24 31 remarks 1. b: byte data, v: vsb (fixed to 32 bits), d: external data bus 2. solid line ( ): write dotted line ( ): read 3. n = 0, 1, 2, 3, ?
preliminary user?s manual a15555ej2v0um 202 appendix a connection example an example of the connection (when a bus master other than the cpu core is not used) of the cpu core, NA85E535, and external memory (sram or sdram) is shown below.
appendix a connection example preliminary user?s manual a15555ej2v0um 203 figure a-1. example of connecting cpu core, NA85E535, and external memory (sram or sdram) (when bus master other than cpu core is not used) sram a25 to a0 d31 to d0 cs sdrasz sdcasz sdwez cke dqm3 to dqm0 sdram a25 to a0 d31 to d0 sdrasz sdcasz sdwez cke dqm3 to dqm0 oe we cpu core vdcsz7 to vdcsz0 vmbenz3 to vmbenz0 vmctyp2 to vmctyp0 vbdo31 to vbdo0 vpresz vmstz vmwait vmahld vma25 to vma0 vmlast vmseq2 to vmseq0 vareq vaack stprq stpak vpubenz vpa13 to vpa0 vpstb vpwrite vpdi15 to vpdi0 phtest phtdo1, phtdo0 phtdin1, phtdin0 vptclk vmwrite NA85E535 vdcsz7 to vdcsz0 vsbenz3 to vsbenz0 vsctyp2 to vsctyp0 vbdi31 to vbdi0 vpresz vsstz vswait vsahld vbclk vsa25 to vsa0 vslast vsseq2 to vsseq0 vaexreq vaack stprq stpak vpubenz vpa13 to vpa0 vpstb vpwrite vpdr15 to vpdr0 phtest phtdo1, phtdo0 phtdin1, phtdin0 vptclk vswrite a25 to a0 di31 to di0 dc3r to dc0r rdzf wrz3 to wrz0 vbclk vbclk busclk asic cs3 cs clk vbdo31 to vbdo0 vpdw15 to vpdw0 vbdi31 to vbdi0 vpdo15 to vpdo0 do31 to do0 csz0 cs0 i/o buffer csz3 vacbrrq rdzr note 3 note 1 iordzr iowrz hldrqz hldakz waitz note 2 selfref note 5 iordzf benz3 to benz0 note 4 note 2 note 1 dc3f to dc0f vpretr vpretr vmlock open note 6 notes 1. used during dma flyby transfer 2. used in bus hold status 3. used for external wait control 4. used when memory with byte enable control function is connected 5. used for self-refresh 6. this may be opened when a bus master other than the cpu core is not used.
preliminary user?s manual a15555ej2v0um 204 appendix b general index [a] a25 to a0 ................................................................. 39 acn1, acn0 ............................................................. 51 address setting wait control register ........................ 51 address/data/chip select controller .......................... 23 asc.......................................................................... 51 astbz ..................................................................... 44 [b] bcc ......................................................................... 52 bcn1, bcn0 ............................................................. 52 bcp.......................................................................... 53 bct0, bct1............................................................. 50 bcw1, bcw0 .......................................................... 59 bcystz ................................................................... 40 benz3 to benz0 ..................................................... 40 bmc ......................................................................... 69 btn1, btn0.............................................................. 50 bunri ...................................................................... 44 bus arbitration controller .......................................... 23 bus cycle control register......................................... 52 bus cycle type configuration registers 0, 1 .............. 50 bus hold function ..................................................... 91 bus mode control register ........................................ 69 busclk................................................................... 41 busclk2................................................................. 41 [c] cke.......................................................................... 41 ckm1, ckm0 ........................................................... 70 ckmd1, ckmd0 ...................................................... 37 connection of unused pins ...................................... 45 control registers....................................................... 48 cpu core connection pins ....................................... 31 csz7 to csz0.......................................................... 40 [d] data flow ................................................................ 187 data flow for byte access (8 bits)........................... 188 data flow for halfword access (16 bits) .................. 190 data flow for word access (32 bits)........................ 196 data read control block ............................................ 23 data wait control registers 0, 1 ................................ 54 data wait control registers and external wait ........... 55 data write control block............................................ 24 dc3f to dc0f..........................................................40 dc3r to dc0r .........................................................40 di31 to di0 ...............................................................39 divider block.............................................................21 dma flyby function....................................................18 dma flyby transfer idle control register.....................75 dma flyby transfer wait control register....................74 dma pins ..................................................................43 dma status signal controller.....................................24 dmactv3 to dmactv0 ..........................................43 dmactvm3 to dmactvm0 ....................................43 dmtco3 to dmtco0 ..............................................43 dmtcom3 to dmtcom0 ........................................43 dmxcsz03 to dmxcsz00 ......................................43 dmxcsz13 to dmxcsz10 ......................................43 dmxczm03 to dmxczm00 .....................................43 dmxczm13 to dmxczm10 .....................................43 dmxtcm03 to dmxtcm00 .....................................43 dmxtcm13 to dmxtcm10 .....................................43 dmxtco03 to dmxtco00......................................43 dmxtco13 to dmxtco10......................................43 do31 to do0............................................................39 dqm3 to dqm0 ........................................................42 dstbz......................................................................44 dwc0, dwc1 ..........................................................54 dwn2 to dwn0.........................................................54 [e] escn ........................................................................64 example of page rom connection...........................78 example of sdram connection ...............................80 example of sram connection..................................76 external memory connection pins ............................39 external wait function ...............................................55 [f] fic............................................................................75 fin1, fin0 .................................................................75 flyby transfer strobe control register........................53 fwc .........................................................................74 fwn2 to fwn0 .........................................................74 [h] hldakz ...................................................................40 hldrqz...................................................................40
appendix b general index preliminary user?s manual a15555ej2v0um 205 [i] initialization pins ...................................................... 37 internal block diagram ............................................. 20 internal bus control block......................................... 24 internal units ............................................................ 21 ioen ........................................................................ 53 iordzf ................................................................... 39 iordzr ................................................................... 39 iowrz..................................................................... 39 [l] lbc0, lbc1............................................................. 67 lbn1, lbn0 .............................................................. 73 lbs .......................................................................... 73 lbs1, lbs0 ............................................................. 38 line buffer control registers 0, 1 .............................. 67 local bus sizing control register .............................. 73 ltm2 to ltm0 ......................................................... 58 [m] ma6 to ma3 ............................................................. 56 mce......................................................................... 37 me7 to me0 ............................................................. 42 memory access timing examples............................. 99 men ......................................................................... 50 mpxcz .................................................................... 44 mpxen .................................................................... 44 mwaitz................................................................... 44 [p] page rom configuration register ............................ 56 page rom connection function ............................... 17 page rom controller ............................................... 21 pdwn...................................................................... 70 phtdin1, phtdin0 ................................................ 44 phtdo1, phtdo0.................................................. 44 phtest................................................................... 44 pin function list......................................................... 28 pin status ................................................................. 46 pins for npb ............................................................ 35 pins for vsb ............................................................ 31 pins reserved by nec ............................................. 44 prc ......................................................................... 56 prw2 to prw0 ....................................................... 56 [r] raw1, raw0 .......................................................... 59 rbn1, rbn0............................................................. 67 rcc1, rcc0............................................................62 rdzf........................................................................39 rdzr .......................................................................39 refrqz...................................................................41 register block ..........................................................21 ren..........................................................................62 rfsn ........................................................................62 rin5 to rin0 ............................................................63 [s] saw1, saw0 ...........................................................59 scrn........................................................................58 sdcasz...................................................................41 sdram configuration register n...............................58 sdram connection function ....................................17 sdram controller.....................................................21 sdram refresh control register n ............................62 sdrasz...................................................................41 sdwez ....................................................................41 selfref .................................................................41 separate unit test function .......................................18 separate unit test mode pins ...................................44 setting register for mobileram expansion mode register n ..................................................................64 speculative read/write buffer function ......................18 sram connection function .......................................17 sram/external i/o controller....................................21 sso1, sso0 ............................................................59 stop function ..........................................................85 stpak......................................................................36 stprq .....................................................................36 symbol diagram .......................................................19 system configuration example .................................25 system control pins..................................................36 [t] tbi0..........................................................................44 tbi1..........................................................................44 tbi2..........................................................................44 tbi3..........................................................................44 tbi9 to tbi4 .............................................................44 tbo15 to tbo0........................................................44 test ........................................................................44 test bus interface block ...........................................24 test function...........................................................186 [v] v2en ..................................................................38, 70
appendix b general index preliminary user?s manual a15555ej2v0um 206 vaack ..................................................................... 33 vacbrrq ............................................................... 33 vaexreq................................................................ 33 variable internal system clock function.................... 18 vbclk ..................................................................... 36 vbclk2 ................................................................... 36 vbdi31 to vbdi0 ..................................................... 32 vbdo31 to vbdo0.................................................. 32 vbresz................................................................... 44 vdcsz7 to vdcsz0................................................ 31 vmlock .................................................................. 33 vpa13 to vpa0........................................................ 35 vpdr15 to vpdr0 .................................................. 35 vpdv ....................................................................... 35 vpdw15 to vpdw0................................................. 35 vpresz................................................................... 32 vpretr................................................................... 35 vpstb ..................................................................... 35 vptclk ................................................................... 44 vpubenz ................................................................ 35 vpwrite................................................................. 35 vsa25 to vsa0........................................................ 31 vsahld................................................................... 34 vsbenz3 to vsbenz0 ........................................... 31 vsctyp2 to vsctyp0 ........................................... 31 vslast ................................................................... 34 vsseq2 to vsseq0 ............................................... 32 vsstz ..................................................................... 33 vswait ................................................................... 34 vswrite................................................................. 33 [w] waitz...................................................................... 39 wcf......................................................................... 58 wrstbz .................................................................. 39 wrstz .................................................................... 42 wrz3 to wrz0........................................................ 39
although nec has taken all possible steps to ensure that the documentation supplied to our customers is complete, bug free and up-to-date, we readily accept that errors may occur. despite all the care and precautions we've taken, you may encounter problems in the documentation. please complete this form whenever you'd like to report errors or suggest improvements to us. hong kong, philippines, oceania nec electronics hong kong ltd. fax: +852-2886-9022/9044 korea nec electronics hong kong ltd. seoul branch fax: +82-2-528-4411 p.r. china nec electronics shanghai, ltd. nec electronics taiwan ltd. fax: +86-21-6841-1137 address north america nec electronics inc. corporate communications dept. fax: +1-800-729-9288 +1-408-588-6130 europe nec electronics (europe) gmbh market communication dept. fax: +49-211-6503-274 south america nec do brasil s.a. fax: +55-11-6462-6829 taiwan asian nations except philippines nec electronics singapore pte. ltd. fax: +886-2-2719-5951 fax: +65-250-3583 japan nec semiconductor technical hotline fax: +81- 44-435-9608 i would like to report the following error/make the following suggestion: document title: document number: page number: thank you for your kind support. if possible, please fax the referenced page or drawing. excellent good acceptable poor document rating clarity technical accuracy organization cs 02.3 name company from: tel. fax facsimile message

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